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hcs08 microcontrollers freescale.com a mc9s08sh8 MC9S08SH4 data sheet mc9s08sh8 rev. 1 11/2007

8-bit hcs08 central processor unit (cpu) 40-mhz hcs08 cpu (central processor unit) hc08 instruction set with added bgnd instruction support for up to 32 interrupt/reset sources on-chip memory flash read/program/erase over full operating voltage and temperature random-access memory (ram) power-saving modes two very low power stop modes reduced power wait mode very low power real time interrupt for use in run, wait, and stop clock source options oscillator (xosc) ?loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16mhz internal clock source (ics) ?internal clock source module containing a frequency-locked loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 2mhz to 20mhz. system protection watchdog computer operating properly (cop) reset with opti/n to run from dedicated 1-khz internal clock source or bus clock low-voltage detection with reset or interrupt; selectable trip points illegal opcode detection with reset illegal address detection with reset flash block protect development support single-wire background debug interface breakpoint capability to allow single breakpoint setting during in-circuit debugging (pluss two more breakpoints in on-chip debug module) on-chip, in-circuit emulation (ice) debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-?w address and event-only data. debug module supports both tag and force breakpoints. peripherals adc ?12-channel, 10-bit resolution, 2.5 s conversion time, automatic compare function, 1.7 mv/ c temperature sensor, internal bandgap reference channel; runs in stop3 acmp ?analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to ?ed internal bandgap reference voltage; output can be optionally routed to tpm module; runs in stop3 sci ?full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge spi ?full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-?st or lsb-?st shifting iic up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing mtim 8-bit modulo counter with 8-bit prescaler and over?w interrupt tpmx ?two 2-channel timer pwm modules (tpm1, tpm2); selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel rtc (real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components, runs in all mcu modes input/output 17 general purpose i/o pins (gpios) and 1 output-only pin 8 interrupt pins with selectable polarity ganged output option for ptb[5:2] and ptc[3:0]; allows single write to change state of multiple pins hysteresis and con?urable pull up device on all input pins; con?urable slew rate and drive strength on all output pins. package options 24-qfn, 20-tssop, 20-pdip, 16-tssop, 8-soic mc9s08sh8 features

preliminary mc9s08sh8 data sheet covers mc9s08sh8 MC9S08SH4 mc9s08sh8 rev. 1 11/2007 freescale and the freescale logo are trademarks of freescale semiconductor, inc. freescale semiconductor, inc., 2007. all rights reserved.
mc9s08sh8 mcu series data sheet, rev. 1 6 freescale semiconductor preliminary revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. revision number revision date description of changes 0.01 3/08/2006 initial review copy 1 11/2007 updated electricals and incorporated revisions from project sync issues: 2394, 2600, 2601, and 2764. freescale semiconductor, inc., 2007. all rights reserved. this product incorporates superflash ? technology licensed from sst.
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 7 list of chapters chapter 1 device overview ...................................................................... 19 chapter 2 pins and connections ............................................................. 23 chapter 3 modes of operation ................................................................. 31 chapter 4 memory ..................................................................................... 37 chapter 5 resets, interrupts, and general system control.................. 59 chapter 6 parallel input/output control.................................................. 75 chapter 7 central processor unit (s08cpuv2) ...................................... 93 chapter 8 analog comparator 5-v (s08acmpv2)................................ 113 chapter 9 analog-to-digital converter (s08adcv1)............................ 121 chapter 10 internal clock source (s08icsv2)........................................ 149 chapter 11 inter-integrated circuit (s08iicv2) ....................................... 163 chapter 12 modulo timer (s08mtimv1).................................................. 181 chapter 13 real-time counter (s08rtcv1) ........................................... 191 chapter 14 serial communications interface (s08sciv4)..................... 201 chapter 15 serial peripheral interface (s08spiv3) ................................ 221 chapter 16 timer pulse-width modulator (s08tpmv3) ......................... 237 chapter 17 development support ........................................................... 263 appendix a electrical characteristics...................................................... 285 appendix b ordering information and mechanical drawings................ 313

mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 9 contents section number title page chapter 1 device overview 1.1 devices in the mc9s08sh8 series ............................................................................................. ....19 1.2 mcu block diagram ........................................................................................................... ...........20 1.3 system clock distribution ................................................................................................... ...........22 chapter 2 pins and connections 2.1 device pin assignment ....................................................................................................... ............23 2.2 recommended system connections .............................................................................................. .24 2.2.1 power ..................................................................................................................... ...........25 2.2.2 oscillator (xosc) ......................................................................................................... ...26 2.2.3 reset .......................................................................................................................... ....26 2.2.4 background / mode select (bkgd/ms) ..........................................................................27 2.2.5 general-purpose i/o and peripheral ports ........................................................................27 chapter 3 modes of operation 3.1 introduction ................................................................................................................ .....................31 3.2 features .................................................................................................................... .......................31 3.3 run mode .................................................................................................................... ....................31 3.4 active background mode ...................................................................................................... ..........31 3.5 wait mode ................................................................................................................... ....................32 3.6 stop modes .................................................................................................................. ....................32 3.6.1 stop3 mode ................................................................................................................ .......33 3.6.2 stop2 mode ................................................................................................................ .......34 3.6.3 on-chip peripheral modules in stop modes ....................................................................34 chapter 4 memory 4.1 mc9s08sh8 memory map ........................................................................................................ ....37 4.2 reset and interrupt vector assignments ...................................................................................... ...38 4.3 register addresses and bit assignments ...................................................................................... ..39 4.4 ram ......................................................................................................................... .......................46 4.5 flash ....................................................................................................................... .....................46 4.5.1 features .................................................................................................................. ...........47 4.5.2 program and erase times .................................................................................................47
mc9s08sh8 mcu series data sheet, rev. 1 10 freescale semiconductor section number title page 4.5.3 program and erase command execution .........................................................................48 4.5.4 burst program execution ..................................................................................................49 4.5.5 access errors ............................................................................................................. .......51 4.5.6 flash block protection ..................................................................................................51 4.5.7 vector redirection ........................................................................................................ ....52 4.6 security .................................................................................................................... ........................52 4.7 flash registers and control bits ............................................................................................ .....53 4.7.1 flash clock divider register (fcdiv) ........................................................................54 4.7.2 flash options register (fopt and nvopt) ................................................................55 4.7.3 flash con?uration register (fcnfg) ........................................................................56 4.7.4 flash protection register (fprot and nvprot) .......................................................56 4.7.5 flash status register (fstat) ......................................................................................57 4.7.6 flash command register (fcmd) ...............................................................................58 chapter 5 resets, interrupts, and general system control 5.1 introduction ................................................................................................................ .....................59 5.2 features .................................................................................................................... .......................59 5.3 mcu reset ................................................................................................................... ...................59 5.4 computer operating properly (cop) watchdog .............................................................................60 5.5 interrupts .................................................................................................................. .......................61 5.5.1 interrupt stack frame ..................................................................................................... ..62 5.5.2 external interrupt request pin (irq) ...............................................................................63 5.5.3 interrupt vectors, sources, and local masks ....................................................................63 5.6 low-voltage detect (lvd) system ............................................................................................. ...65 5.6.1 power-on reset operation ...............................................................................................65 5.6.2 low-voltage detection (lvd) reset operation ...............................................................65 5.6.3 low-voltage warning (lvw) interrupt operation ...........................................................65 5.7 reset, interrupt, and system control registers and control bits ...................................................65 5.7.1 interrupt pin request status and control register (irqsc) ............................................66 5.7.2 system reset status register (srs) .................................................................................67 5.7.3 system background debug force reset register (sbdfr) ............................................68 5.7.4 system options register 1 (sopt1) ................................................................................69 5.7.5 system options register 2 (sopt2) ................................................................................70 5.7.6 system device identi?ation register (sdidh, sdidl) ................................................71 5.7.7 system power management status and control 1 register (spmsc1) ...........................72 5.7.8 system power management status and control 2 register (spmsc2) ...........................73 chapter 6 parallel input/output control 6.1 port data and data direction ................................................................................................ ..........75 6.2 pull-up, slew rate, and drive strength ...................................................................................... .....76
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 11 section number title page 6.3 ganged output ............................................................................................................... .................77 6.4 pin interrupts .............................................................................................................. .....................78 6.4.1 edge only sensitivity ..................................................................................................... ..78 6.4.2 edge and level sensitivity ................................................................................................78 6.4.3 pull-up/pull-down resistors .............................................................................................79 6.4.4 pin interrupt initialization .............................................................................................. ...79 6.5 pin behavior in stop modes .................................................................................................. ..........79 6.6 parallel i/o and pin control registers ...................................................................................... ......79 6.6.1 port a registers .......................................................................................................... ......80 6.6.2 port b registers .......................................................................................................... ......85 6.6.3 port c registers .......................................................................................................... ......89 chapter 7 central processor unit (s08cpuv2) 7.1 introduction ................................................................................................................ .....................93 7.1.1 features .................................................................................................................. ...........93 7.2 programmers model and cpu registers .......................................................................................94 7.2.1 accumulator (a) ........................................................................................................... ....94 7.2.2 index register (h:x) ...................................................................................................... ...94 7.2.3 stack pointer (sp) ........................................................................................................ .....95 7.2.4 program counter (pc) ......................................................................................................95 7.2.5 condition code register (ccr) .......................................................................................95 7.3 addressing modes ............................................................................................................ ...............97 7.3.1 inherent addressing mode (inh) .....................................................................................97 7.3.2 relative addressing mode (rel) .....................................................................................97 7.3.3 immediate addressing mode (imm) ................................................................................97 7.3.4 direct addressing mode (dir) ........................................................................................97 7.3.5 extended addressing mode (ext) ..................................................................................98 7.3.6 indexed addressing mode ................................................................................................98 7.4 special operations .......................................................................................................... .................99 7.4.1 reset sequence ............................................................................................................ .....99 7.4.2 interrupt sequence ........................................................................................................ ....99 7.4.3 wait mode operation ......................................................................................................100 7.4.4 stop mode operation ......................................................................................................100 7.4.5 bgnd instruction .......................................................................................................... .101 7.5 hcs08 instruction set summary ............................................................................................... ...102 chapter 8 analog comparator 5-v (s08acmpv2) 8.1 introduction ................................................................................................................ ...................113 8.1.1 acmp con?uration information ..................................................................................113 8.1.2 acmp in stop3 mode .....................................................................................................113
mc9s08sh8 mcu series data sheet, rev. 1 12 freescale semiconductor section number title page 8.1.3 acmp/tpm con?uration information .........................................................................113 8.1.4 features .................................................................................................................. .........115 8.1.5 modes of operation ........................................................................................................115 8.1.6 block diagram ............................................................................................................. ...115 8.2 external signal description ................................................................................................. .........117 8.3 memory map .................................................................................................................. ..............117 8.3.1 register descriptions ..................................................................................................... .117 8.4 functional description ...................................................................................................... ............119 chapter 9 analog-to-digital converter (s08adcv1) 9.1 introduction ................................................................................................................ ...................121 9.1.1 channel assignments ......................................................................................................121 9.1.2 alternate clock ........................................................................................................... ....122 9.1.3 hardware trigger .......................................................................................................... ..122 9.1.4 temperature sensor ........................................................................................................122 9.1.5 features .................................................................................................................. .........125 9.1.6 block diagram ............................................................................................................. ...125 9.2 external signal description ................................................................................................. .........126 9.2.1 analog power (v ddad ) ..................................................................................................127 9.2.2 analog ground (v ssad ) .................................................................................................127 9.2.3 voltage reference high (v refh ) ...................................................................................127 9.2.4 voltage reference low (v refl ) .....................................................................................127 9.2.5 analog channel inputs (adx) ........................................................................................127 9.3 register de?ition .......................................................................................................... ..............127 9.3.1 status and control register 1 (adcsc1) ......................................................................127 9.3.2 status and control register 2 (adcsc2) ......................................................................129 9.3.3 data result high register (adcrh) .............................................................................130 9.3.4 data result low register (adcrl) ..............................................................................130 9.3.5 compare value high register (adccvh) ....................................................................131 9.3.6 compare value low register (adccvl) .....................................................................131 9.3.7 con?uration register (adccfg) ................................................................................131 9.3.8 pin control 1 register (apctl1) ..................................................................................133 9.3.9 pin control 2 register (apctl2) ..................................................................................134 9.3.10 pin control 3 register (apctl3) ..................................................................................135 9.4 functional description ...................................................................................................... ............136 9.4.1 clock select and divide control ....................................................................................136 9.4.2 input select and pin control ...........................................................................................137 9.4.3 hardware trigger .......................................................................................................... ..137 9.4.4 conversion control ........................................................................................................ .137 9.4.5 automatic compare function .........................................................................................140 9.4.6 mcu wait mode operation ............................................................................................140
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 13 section number title page 9.4.7 mcu stop3 mode operation ..........................................................................................140 9.4.8 mcu stop1 and stop2 mode operation .........................................................................141 9.5 initialization information .................................................................................................. ............141 9.5.1 adc module initialization example .............................................................................141 9.6 application information ..................................................................................................... ...........143 9.6.1 external pins and routing ..............................................................................................143 9.6.2 sources of error .......................................................................................................... ....145 chapter 10 internal clock source (s08icsv2) 10.1 introduction ............................................................................................................... ....................149 10.1.1 module con?uration .....................................................................................................149 10.1.2 features ................................................................................................................. ..........151 10.1.3 block diagram ............................................................................................................ ....151 10.1.4 modes of operation ....................................................................................................... .152 10.2 external signal description ................................................................................................ ..........153 10.3 register de?ition ......................................................................................................... ...............153 10.3.1 ics control register 1 (icsc1) .....................................................................................154 10.3.2 ics control register 2 (icsc2) .....................................................................................155 10.3.3 ics trim register (icstrm) .........................................................................................156 10.3.4 ics status and control (icssc) .....................................................................................156 10.4 functional description ..................................................................................................... .............157 10.4.1 operational modes ........................................................................................................ ..157 10.4.2 mode switching ........................................................................................................... ...159 10.4.3 bus frequency divider ...................................................................................................160 10.4.4 low power bit usage .....................................................................................................160 10.4.5 internal reference clock ................................................................................................160 10.4.6 optional external reference clock ................................................................................160 10.4.7 fixed frequency clock ...................................................................................................161 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction ............................................................................................................... ....................163 11.1.1 module con?uration .....................................................................................................163 11.1.2 features ................................................................................................................. ..........165 11.1.3 modes of operation ....................................................................................................... .165 11.1.4 block diagram ............................................................................................................ ....165 11.2 external signal description ................................................................................................ ..........166 11.2.1 scl ?serial clock line ...............................................................................................166 11.2.2 sda ?serial data line ................................................................................................166 11.3 register de?ition ......................................................................................................... ...............166 11.3.1 iic address register (iica) ...........................................................................................167
mc9s08sh8 mcu series data sheet, rev. 1 14 freescale semiconductor section number title page 11.3.2 iic frequency divider register (iicf) ...........................................................................167 11.3.3 iic control register (iicc1) ..........................................................................................170 11.3.4 iic status register (iics) ...............................................................................................170 11.3.5 iic data i/o register (iicd) ..........................................................................................171 11.3.6 iic control register 2 (iicc2) .......................................................................................172 11.4 functional description ..................................................................................................... .............173 11.4.1 iic protocol ............................................................................................................. ........173 11.4.2 10-bit address ........................................................................................................... ......176 11.4.3 general call address ..................................................................................................... .177 11.5 resets ..................................................................................................................... .......................177 11.6 interrupts ................................................................................................................. ......................177 11.6.1 byte transfer interrupt .................................................................................................. ..177 11.6.2 address detect interrupt .................................................................................................178 11.6.3 arbitration lost interrupt ............................................................................................... .178 11.7 initialization/application information ..................................................................................... .....179 chapter 12 modulo timer (s08mtimv1) 12.1 introduction ............................................................................................................... ....................181 12.1.1 mtim con?uration information ..................................................................................181 12.1.2 features ................................................................................................................. ..........183 12.1.3 modes of operation ....................................................................................................... .183 12.1.4 block diagram ............................................................................................................ ....184 12.2 external signal description ................................................................................................ ..........184 12.3 register de?ition ......................................................................................................... ...............185 12.3.1 mtim status and control register (mtimsc) .............................................................186 12.3.2 mtim clock con?uration register (mtimclk) .......................................................187 12.3.3 mtim counter register (mtimcnt) ...........................................................................188 12.3.4 mtim modulo register (mtimmod) ..........................................................................188 12.4 functional description ..................................................................................................... .............189 12.4.1 mtim operation example .............................................................................................190 chapter 13 real-time counter (s08rtcv1) 13.1 introduction ............................................................................................................... ....................191 13.1.1 features ................................................................................................................. ..........193 13.1.2 modes of operation ....................................................................................................... .193 13.1.3 block diagram ............................................................................................................ ....194 13.2 external signal description ................................................................................................ ..........194 13.3 register de?ition ......................................................................................................... ...............194 13.3.1 rtc status and control register (rtcsc) ....................................................................195 13.3.2 rtc counter register (rtccnt) ..................................................................................196
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 15 section number title page 13.3.3 rtc modulo register (rtcmod) ................................................................................196 13.4 functional description ..................................................................................................... .............196 13.4.1 rtc operation example .................................................................................................197 13.5 initialization/application information ..................................................................................... .....198 chapter 14 serial communications interface (s08sciv4) 14.1 introduction ............................................................................................................... ....................201 14.1.1 features ................................................................................................................. ..........203 14.1.2 modes of operation ....................................................................................................... .203 14.1.3 block diagram ............................................................................................................ ....204 14.2 register de?ition ......................................................................................................... ...............206 14.2.1 sci baud rate registers (scixbdh, scixbdl) ..........................................................206 14.2.2 sci control register 1 (scixc1) ...................................................................................207 14.2.3 sci control register 2 (scixc2) ...................................................................................208 14.2.4 sci status register 1 (scixs1) ......................................................................................209 14.2.5 sci status register 2 (scixs2) ......................................................................................211 14.2.6 sci control register 3 (scixc3) ...................................................................................212 14.2.7 sci data register (scixd) .............................................................................................213 14.3 functional description ..................................................................................................... .............213 14.3.1 baud rate generation .....................................................................................................213 14.3.2 transmitter functional description ................................................................................214 14.3.3 receiver functional description .....................................................................................215 14.3.4 interrupts and status flags ..............................................................................................217 14.3.5 additional sci functions ...............................................................................................218 chapter 15 serial peripheral interface (s08spiv3) 15.1 introduction ............................................................................................................... ....................221 15.1.1 features ................................................................................................................. ..........223 15.1.2 block diagrams ........................................................................................................... ...223 15.1.3 spi baud rate generation ..............................................................................................225 15.2 external signal description ................................................................................................ ..........226 15.2.1 spsck ?spi serial clock ............................................................................................226 15.2.2 mosi ?master data out, slave data in ......................................................................226 15.2.3 miso ?master data in, slave data out ......................................................................226 15.2.4 ss ?slave select ...........................................................................................................226 15.3 modes of operation ......................................................................................................... ..............227 15.3.1 spi in stop modes ........................................................................................................ ..227 15.4 register de?ition ......................................................................................................... ...............227 15.4.1 spi control register 1 (spic1) ......................................................................................227 15.4.2 spi control register 2 (spic2) ......................................................................................228
mc9s08sh8 mcu series data sheet, rev. 1 16 freescale semiconductor section number title page 15.4.3 spi baud rate register (spibr) ....................................................................................229 15.4.4 spi status register (spis) ..............................................................................................230 15.4.5 spi data register (spid) ................................................................................................231 15.5 functional description ..................................................................................................... .............232 15.5.1 spi clock formats ........................................................................................................ ..232 15.5.2 spi interrupts ........................................................................................................... .......235 15.5.3 mode fault detection .....................................................................................................235 chapter 16 timer pulse-width modulator (s08tpmv3) 16.1 introduction ............................................................................................................... ....................237 16.1.1 acmp/tpm con?uration information .........................................................................237 16.1.2 tpm con?uration information .....................................................................................237 16.1.3 features ................................................................................................................. ..........239 16.1.4 modes of operation ....................................................................................................... .239 16.1.5 block diagram ............................................................................................................ ....240 16.2 signal description ......................................................................................................... ................242 16.2.1 detailed signal descriptions ...........................................................................................242 16.3 register de?ition ......................................................................................................... ...............246 16.3.1 tpm status and control register (tpmxsc) ................................................................246 16.3.2 tpm-counter registers (tpmxcnth:tpmxcntl) ....................................................247 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) ....................................248 16.3.4 tpm channel n status and control register (tpmxcnsc) ..........................................249 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) ..........................................251 16.4 functional description ..................................................................................................... .............252 16.4.1 counter .................................................................................................................. ..........253 16.4.2 channel mode selection .................................................................................................255 16.5 reset overview ............................................................................................................. ................258 16.5.1 general .................................................................................................................. ..........258 16.5.2 description of reset operation .......................................................................................258 16.6 interrupts ................................................................................................................. ......................258 16.6.1 general .................................................................................................................. ..........258 16.6.2 description of interrupt operation ..................................................................................259 16.7 differences between tpm v2 to tpm v3 .....................................................................................260 chapter 17 development support 17.1 introduction ............................................................................................................... ....................263 17.1.1 forcing active background ............................................................................................263 17.1.2 features ................................................................................................................. ..........264 17.2 background debug controller (bdc) ..........................................................................................264 17.2.1 bkgd pin description ...................................................................................................265
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 17 section number title page 17.2.2 communication details ..................................................................................................266 17.2.3 bdc commands .............................................................................................................270 17.2.4 bdc hardware breakpoint .............................................................................................272 17.3 on-chip debug system (dbg) ................................................................................................. ...273 17.3.1 comparators a and b ......................................................................................................273 17.3.2 bus capture information and fifo operation ...............................................................273 17.3.3 change-of-flow information ..........................................................................................274 17.3.4 tag vs. force breakpoints and triggers .........................................................................274 17.3.5 trigger modes ............................................................................................................ .....275 17.3.6 hardware breakpoints ....................................................................................................277 17.4 register de?ition ......................................................................................................... ...............277 17.4.1 bdc registers and control bits .....................................................................................277 17.4.2 system background debug force reset register (sbdfr) ..........................................279 17.4.3 dbg registers and control bits .....................................................................................280 appendix a electrical characteristics a.1 introduction ................................................................................................................ ...................285 a.2 parameter classification .................................................................................................... ............285 a.3 absolute maximum ratings .................................................................................................... ......285 a.4 thermal characteristics ..................................................................................................... ............287 a.5 esd protection and latch-up immunity ......................................................................................289 a.6 dc characteristics .......................................................................................................... ...............290 a.7 supply current characteristics .............................................................................................. ........294 a.8 external oscillator (xosc) characteristics .................................................................................297 a.9 internal clock source (ics) characteristics .................................................................................299 a.10 analog comparator (acmp) electricals ......................................................................................300 a.11 adc characteristics ........................................................................................................ ..............301 a.12 ac characteristics ......................................................................................................... ................304 a.12.1 control timing ........................................................................................................... ....304 a.12.2 tpm/mtim module timing ..........................................................................................306 a.12.3 spi ...................................................................................................................... .............307 a.13 flash specifications ....................................................................................................... ............310 a.14 emc performance ............................................................................................................ .............311 a.14.1 radiated emissions ....................................................................................................... ..311 a.14.2 conducted transient susceptibility ................................................................................311 appendix b ordering information and mechanical drawings b.1 ordering information ........................................................................................................ ............313 b.1.1 device numbering scheme ............................................................................................313 b.2 mechanical drawings ......................................................................................................... ...........314

mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 19 chapter 1 device overview the mc9s08sh8 members of the low-cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced hcs08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 devices in the mc9s08sh8 series table 1-1 summarizes the feature set available in the mc9s08sh8 series of mcus. t table 1-1. mc9s08sh8 features by mcu and package feature 9s08sh8 9s08sh4 flash size (bytes) 8192 4096 ram size (bytes) 512 256 pin quantity 24 20 16 8 24 20 16 8 acmp yes adc channels 12 12 8 4 12 12 8 4 dbg yes ics yes yes yes yes 1 1 fbe and fee modes are not available in 8-pin packages. yes yes yes yes 1 iic yes mtim yes pin interrupts 8 8 8 4 8 8 8 4 pin i/o 2 2 port i/o count does not include the output-only pta4/acmpo/bkgd/ms. 17 17 13 5 17 17 13 5 rtc yes sci yes yes yes no yes yes yes no spi yes yes yes no yes yes yes no tpm1 channels 2 2 2 1 2 2 2 1 tpm2 channels 2 2 2 1 2 2 2 1 xosc yes yes yes no yes yes yes no
chapter 1 device overview mc9s08sh8 mcu series data sheet, rev. 1 20 freescale semiconductor 1.2 mcu block diagram the block diagram in figure 1-1 shows the structure of the mc9s08sh8 mcu. figure 1-1. mc9s08sh8 block diagram ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 1 device overview mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 21 table 1-2 provides the functional version of the on-chip modules table 1-2. module versions module version analog comparator (5v) (acmp) 2 analog-to-digital converter (adc) 1 central processor unit (cpu) 2 inter-integrated circuit (iic) 2 internal clock source (ics) 2 serial peripheral interface (spi) 3 serial communications interface (sci) 4 modulo timer (mtim) 1 real-time counter (rtc) 1 timer pulse width modulator (tpm) 3
chapter 1 device overview mc9s08sh8 mcu series data sheet, rev. 1 22 freescale semiconductor 1.3 system clock distribution figure 1-2 shows a simpli?d clock connection diagram. some modules in the mcu have selectable clock inputs as shown. the clock inputs to the modules indicate the clock(s) that are used to drive the module function. the following de?es the clocks used in this mcu: busclk ?the frequency of the bus is always half of icsout. icsout ?primary output of the ics and is twice the bus frequency. icslclk development tools can select this clock source to speed up bdc communications in systems where the bus clock is con?ured to run at a very slow frequency. icserclk ?external reference clock can be selected as the rtc clock source and as the alternate clock for the adc module. icsirclk ?internal reference clock can be selected as the rtc clock source. icsffclk ?fixed frequency clock can be selected as clock source for the tpm1, tpm2 and mtim modules. lpoclk independent 1-khz clock source that can be selected as the clock source for the cop and rtc modules. tclk external input clock source for tpm1, tpm2 and mtim and is referenced as tpmclk in tpm chapters. figure 1-2. system clock distribution diagram tpm1 tpm2 mtim sci bdc cpu adc iic flash ics icsout 2 busclk icslclk icserclk cop * the ?ed frequency clock (ffclk) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. flash has frequency requirements for program and erase operation. see the electricals appendix for details. adc has min and max frequency requirements. see the adc chapter and electricals appendix for details. xosc extal xtal spi ffclk* icsffclk rtc 1 khz lpo tclk icsirclk 2 sync* lpoclk
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 23 chapter 2 pins and connections this section describes signals that connect to package pins. it includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 device pin assignment figure 2-1 - figure 2-4 shows the pin assignments for the mc9s08sh8 devices. figure 2-1. 24-pin qfn pta5/irq/tclk/ reset pta4/acmpo/bkgd/ms v dd v ss ptb4/tpm2ch1/miso ptb5/tpm1ch1/ ss ptb6/sda/xtal ptb7/scl/extal ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 ptb1/pib1/txd/adp5 pta1/pia1/tpm2ch0/adp1/acmp pta2/pia2/sda/adp2 pta3/pia3/scl/adp3 ptb0/pib0/rxd/adp4 pta0/pia0/tpm1ch0adp0/acmp+ pin 1 indicator 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 101112 24 23 22 21 20 19 ptc3/adp11 ptc2/adp10 ptc1/tpmch1/adp9 ptc0/tpm1ch0/adp8 nc nc nc nc
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 24 freescale semiconductor figure 2-2. 20-pin pdip and tssop figure 2-3. 16-pin tssop figure 2-4. 8-pin soic 2.2 recommended system connections figure 2-5 shows pin connections that are common to mc9s08sh8 application systems. ptb1/pib1/txd/adp5 ptb5/tpm1ch1/ ss ptb6/sda/xtal ptb2/pib2/spsck/adp6 pta3/pia3/scl/adp3 ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb0/pib0/rxd/adp4 v dd v ss ptb7/scl/extal 1 2 3 4 5 6 7 8 20 19 18 17 16 15 9 10 14 12 11 13 ptc3/adp11 ptc0/tpm1ch0/adp8 ptc2/adp10 ptc1/tpm1ch1/adp9 pta4/acmpo/ bkgd/ms pta5/irq/tclk/ reset pta2/pia2/sda/adp2 pta1/pia1/tpm2ch0/adp1/acmp- pta0/pia0/tpm1ch0/adp0/acmp+ ptb1/pib1/txd/adp5 ptb5/tpm1ch1/ ss ptb6/sda/xtal ptb2/pib2/spsck/adp6 pta3/pia3/scl/adp3 ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb0/pib0/rxd/adp4 v dd v ss ptb7/scl/extal 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pta4/acmpo/ bkgd/ms pta5/irq/tclk/ reset pta2/pia2/sda/adp2 pta1/pia1/tpm2ch0/adp1/acmp- pta0/pia0/tpm1ch0/adp0/acmp+ 1 2 3 4 8 7 6 5 pta0/pia0/tpm1ch0/adp0/acmp+ pta1/pia1/tpm2ch0/adp1/acmp- pta2/pia2/sda/adp2 pta3/pia3/scl/adp3 v ss v dd pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 25 figure 2-5. basic system connections 2.2.1 power v dd and v ss are the primary power supply pins for the mcu. this voltage source supplies power to all i/o buffer circuitry, acmp and adc modules, and to an internal voltage regulator. the internal voltage regulator provides regulated lower-voltage source to the cpu and other internal circuitry of the mcu. typically, application systems have two separate capacitors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as near to the mcu power pins as practical to suppress high-frequency noise. each pin must have a bypass capacitor for best noise suppression. bkgd/ms reset optional manual reset v dd background header system power port b ptb0/pib0/rxd/adp4 ptb1/pib1/txd/adp5 ptb2/pib2/spsck/adp6 ptb3/pib3/mosi/adp7 ptb4/tpm2ch1/miso ptb5/tpm1ch1/ ss ptb6/sda/xtal ptb7/scl/extal port c ptc0/tpm1ch0/adp8 ptc1/tpm1ch1/adp9 ptc2/adp10 ptc3/adp11 mc9s08sh8 v ss v dd c by 0.1 f c blk 10 f + 5 v + c2 c1 x1 r f r s port a pta0/pia0/tpm1ch0/adp0/acmp+ pta1/pia1/tpm2ch0/adp1/acmp- pta2/pia2/sda/adp2 pta3/pia3/scl/adp3 0.1 f v dd 4.7 k ?0 k note 1 notes: 1. external crystal circuit not required if using the internal clock option. 2. reset pin can only be used to reset into user mode, you can not enter bdm using reset pin. bdm can be entered by holding ms low during por or writing a 1 to bdfr in sbdfr with ms low after issuing bdm command. 3. rc filter on reset pin recommended for noisy environments. pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 26 freescale semiconductor 2.2.2 oscillator (xosc) immediately after reset, the mcu uses an internally generated clock provided by the clock source generator (ics) module. for more information on the ics, see chapter 10, ?nternal clock source (s08icsv2). the oscillator (xosc) in this mcu is a pierce oscillator that can accommodate a crystal or ceramic resonator. rather than a crystal or ceramic resonator, an external oscillator can be connected to the extal input pin. refer to figure 2-5 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resistors, and some metal ?m resistors, have too much inductance. c1 and c2 normally should be high-quality ceramic capacitors that are speci?ally designed for high-frequency applications. r f is used to provide a bias path to keep the extal input in its linear range during crystal startup; its value is not generally critical. typical systems use 1 m to 10 m . higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a speci? crystal or resonator. be sure to take into account printed circuit board (pcb) capacitance and mcu pin capacitance when selecting c1 and c2. the crystal manufacturer typically speci?s a load capacitance which is the series combination of c1 and c2 (which are usually the same size). as a ?st-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal). 2.2.3 reset after a power-on reset (por), the pta5/irq/tclk/ reset pin defaults to a general-purpose i/o port pin, pta5. setting rstpe in sopt1 con?ures the pin to be the reset pin with an open-drain drive containing an internal pull-up device. after con?ured as reset, the pin will remain reset until the next por. the reset pin when enabled can be used to reset the mcu from an external source when the pin is driven low. internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. this pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any non-por reset is initiated (whether from an external signal or from an internal system), the reset pin if enabled is driven low for about 66 bus cycles. the reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (srs). note this pin does not contain a clamp diode to v dd and should not be driven above v dd .
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 27 the voltage measured on the internally pulled up reset pin will not be pulled to v dd . the internal gates connected to this pin are pulled to v dd .if the reset pin is required to drive to a v dd level an external pullup should be used. note in emc-sensitive applications, an external rc ?ter is recommended on the reset. see figure 2-5 for an example. 2.2.4 background / mode select (bkgd/ms) during a power-on-reset (por) or background debug force reset (see section 5.7.3, ?ystem background debug force reset register (sbdfr) ,?for more information), the pta4/acmpo/bkgd/ms pin functions as a mode select pin. immediately after any reset, the pin functions as the background pin and can be used for background debug communication. when enabled as the bkgd/ms pin (bkgdpe = 1), an internal pullup device is automatically enabled. the background debug communication function is enabled when bkgdpe in sopt1 is set. bkgdpe is set following any reset of the mcu and must be cleared to use the pta4/acmpo/bkgd/ms pins alternative pin function. if nothing is connected to this pin, the mcu will enter normal operating mode at the rising edge of the internal reset after a por or force bdc reset. if a debug system is connected to the 6-pin standard background debug header, it can hold bkgd/ms low during a por or immediately after issuing a background debug force reset, which will force the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communications using a custom protocol that uses 16 clock cycles of the target mcus bdc clock per bit time. the target mcus bdc clock could be as fast as the maximum bus clock rate, so there must never be any signi?ant capacitance connected to the bkgd/ms pin that could interfere with background serial communications. although the bkgd pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the bkgd pin. 2.2.5 general-purpose i/o and peripheral ports the mc9s08sh8 series of mcus support up to 17 general-purpose i/o pins and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial i/o, adc, etc). when a port pin is con?ured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. when a port pin is con?ured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. immediately after reset, all of these pins are con?ured as high-impedance general-purpose inputs with internal pull-up devices disabled.
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 28 freescale semiconductor when an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pins output buffer. for information about controlling these pins as general-purpose i/o pins, see chapter 6, ?arallel input/output control . the mc9s08sh8 devices contain a ganged output drive feature that allows a safe and reliable method of allowing pins to be tied together externally to produce a higher output current drive. see section 6.3, ?anged output ?for more information for con?uring the port pins for ganged output drive. note to avoid extra current drain from ?ating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused pins to outputs so they do not ?at. when using the 8-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out port b and port c pins to outputs so the pins do not ?at. when using the 16-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out port c pins to outputs so the pins do not ?at.
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 29 pin number priority 24-pin 20-pin 16-pin 8-pin port pin alt 1 alt 2 alt 3 alt 4 alt5 1333 v dd 2 3444 v ss 4 5 5 ptb7 scl 1 1 iic pins can be repositioned using iicps in sopt2, default reset locations are on pta2 and pta3. extal 5 6 6 ptb6 sda 1 xtal 6 7 7 ptb5 tpm1ch1 2 2 tpm1chx pins can be repositioned using tpm1ps in sopt2, default reset locations are on pta0 and ptb5. ss ptc0 3 3 this port pin is part of the ganged output feature. when pin is enabled for ganged output, it will have priority over all digital modules. the output data, drive strength and slew-rate control of this port pin will follow the con?uration for the ptc0 pin, even in 16-pin packages where ptc0 doesn? bond out. ganged output not available in 8-pin packages. 7 8 8 ptb4 tpm2ch1 miso ptc0 3 8 9 ptc3 ptc0 3 adp11 9 10 ptc2 ptc0 3 adp10 10 11 ptc1 tpm1ch1 2 ptc0 3 adp9 11 12 ptc0 tpm1ch0 2 ptc0 3 adp8 12 13 9 ptb3 pib3 mosi ptc0 3 adp7 13 14 10 ptb2 pib2 spsck ptc0 3 adp6 14 15 11 ptb1 pib1 txd adp5 15 16 12 ptb0 pib0 rxd adp4 16 17 13 5 pta3 pia3 scl 1 adp3 17 18 14 6 pta2 pia2 sda 1 adp2 18 19 15 7 pta1 pia1 tpm2ch0 adp1 4 4 if acmp and adc are both enabled, both will have access to the pin. acmp 4 19 20 16 8 pta0 pia0 tpm1ch0 2 adp0 4 acmp+ 4 20 21 22 23 1 1 1 pta5 5 irq tclk reset 24 2 2 2 pta4 acmpo bkgd ms 5 pin is open-drain when con?ured as output driving high. pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up reset will not be pulled to v dd . the internal gates connected to this pin are pulled to v dd . lowest highest table 2-1. pin availability by package pin-count
chapter 2 pins and connections mc9s08sh8 mcu series data sheet, rev. 1 30 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 31 chapter 3 modes of operation 3.1 introduction the operating modes of the mc9s08sh8 are described in this chapter. entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 features active background mode for code development wait mode ?cpu shuts down to conserve power; system clocks are running and full regulation is maintained stop modes ?system clocks are stopped and voltage regulator is in standby stop3 ?all internal circuits are powered for fast recovery stop2 ?partial power down of internal circuits, ram content is retained 3.3 run mode this is the normal operating mode for the mc9s08sh8. this mode is selected upon the mcu exiting reset if the bkgd/ms pin is high. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at 0xfffe?xffff after reset. 3.4 active background mode the active background mode functions are managed through the background debug controller (bdc) in the hcs08 core. the bdc, together with the on-chip debug module (dbg), provide the means for analyzing mcu operation during software development. active background mode is entered in any of the following ways: when the bkgd/ms pin is low during por or immediately after issuing a background debug force reset (see section 5.7.3, ?ystem background debug force reset register (sbdfr) ? when a background command is received through the bkgd/ms pin when a bgnd instruction is executed when encountering a bdc breakpoint when encountering a dbg breakpoint after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program.
chapter 3 modes of operation mc9s08sh8 mcu series data sheet, rev. 1 32 freescale semiconductor background commands are of two types: non-intrusive commands, de?ed as commands that can be issued while the user program is running. non-intrusive commands can be issued through the bkgd/ms pin while the mcu is in run mode; non-intrusive commands can also be executed when the mcu is in the active background mode. non-intrusive commands include: memory access commands memory-access-with-status commands bdc register access commands the background command active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: read or write cpu registers trace one user program instruction at a time leave active background mode to return to the user application program (go) the active background mode is used to program a bootloader or user application program into the flash program memory before the mcu is operated in run mode for the ?st time. when the mc9s08sh8 is shipped from the freescale semiconductor factory, the flash program memory is erased by default unless speci?ally noted so there is no program that could be executed in run mode until the flash memory is initially programmed. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to the development support chapter. 3.5 wait mode wait mode is entered by executing a wait instruction. upon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background command and memory-access-with-status commands are available when the mcu is in wait mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode. 3.6 stop modes one of two stop modes is entered upon execution of a stop instruction when stope in sopt1. in any stop mode, the bus and cpu clocks are halted. the ics module can be con?ured to leave the reference clocks running. see chapter 10, ?nternal clock source (s08icsv2) ,?for more information.
chapter 3 modes of operation mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 33 table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. the selected mode is entered following the execution of a stop instruction. 3.6.1 stop3 mode stop3 mode is entered by executing a stop instruction under the conditions as shown in table 3-1 . the states of all of the internal registers and logic, ram contents, and i/o pin states are maintained. stop3 can be exited by asserting reset if enabled, or by an interrupt from one of the following sources: the real-time counter (rtc), lvd system, acmp, adc, sci, irq, or any pin interrupts. if stop3 is exited by means of the reset pin, then the mcu is reset and operation will resume after taking the reset vector. exit by means of one of the internal interrupt sources results in the mcu taking the appropriate interrupt vector. 3.6.1.1 lvd enabled in stop mode the lvd system is capable of generating either an interrupt or a reset when the supply voltage drops below the lvd voltage. for con?uring the lvd system for interrupt or reset, refer to 5.6, ?ow-voltage detect (lvd) system ? if the lvd is enabled in stop (lvde and lvdse bits in spmsc1 both set) at the time the cpu executes a stop instruction, then the voltage regulator remains active during stop mode. for the adc to operate in stop mode, the lvd must be enabled when entering stop3. for the acmp to operate in stop mode with compare to internal bandgap option, the lvd must be enabled when entering stop3. 3.6.1.2 active bdm enabled in stop mode entry into the active background mode from run mode is enabled if enbdm in bdcscr is set. this register is described in chapter 17, ?evelopment support .?if enbdm is set when the cpu executes a stop instruction, the system clocks to the background debug logic remain active when the mcu enters stop mode. because of this, background debug communication remains possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. table 3-1. stop mode selection stope enbdm 1 1 enbdm is located in the bdcscr, which is only accessible through bdc commands, see section 17.4.1.1, ?dc status and control register (bdcscr)? lvde lvdse ppdc stop mode 0 x x x stop modes disabled; illegal opcode reset if stop instruction executed 1 1 x x stop3 with bdm enabled 2 2 when in stop3 mode with bdm enabled, the s idd will be near r idd levels because internal clocks are enabled. 1 0 both bits must be 1 0 stop3 with voltage regulator active 1 0 either bit a 0 0 stop3 1 0 either bit a 0 1 stop2
chapter 3 modes of operation mc9s08sh8 mcu series data sheet, rev. 1 34 freescale semiconductor most background commands are not available in stop mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. after entering background debug mode, all background commands are available. 3.6.2 stop2 mode stop2 mode is entered by executing a stop instruction under the conditions as shown in table 3-1 . most of the internal circuitry of the mcu is powered off in stop2 with the exception of the ram. upon entering stop2, all i/o pin control signals are latched so that the pins retain their states during stop2. exit from stop2 is performed by asserting the wake-up pin (pta5/irq/tclk/ reset) on the mcu. in addition, the real-time counter (rtc) can wake the mcu from stop2, if enabled. upon wake-up from stop2 mode, the mcu starts up as from a power-on reset (por): all module control and status registers are reset the lvd reset function is enabled and the mcu remains in the reset state if v dd is below the lvd trip point (low trip point selected due to por) the cpu takes the reset vector in addition to the above, upon waking up from stop2, the ppdf bit in spmsc2 is set. this ?g is used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a 1 is written to ppdack in spmsc2. to maintain i/o states for pins that were con?ured as general-purpose i/o before entering stop2, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the pins will switch to their reset states when ppdack is written. for pins that were con?ured as peripheral i/o, the user must recon?ure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.3 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal peripheral modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. refer to section 3.6.2, ?top2 mode ,?and section 3.6.1, ?top3 mode ,?for speci? information on system behavior in stop modes.
chapter 3 modes of operation mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 35 table 3-2. stop mode behavior peripheral mode stop2 stop3 cpu off standby ram standby standby flash off standby parallel port registers off standby adc off optionally on 1 1 requires the asynchronous adc clock and lvd to be enabled, else in standby. acmp off optionally on 2 2 requires the lvd to be enabled when compare to internal bangap reference option is enabled. bdm off 3 3 if enbdm is set when entering stop2, the mcu will actually enter stop3.. optionally on ics off optionally on 4 4 irclken and irefsten set in icsc1, else in standby. iic off standby lvd/lvw off 5 5 if lvdse is set when entering stop2, the mcu will actually enter stop3.. optionally on mtim off standby rtc optionally on optionally on sci off standby spi off standby tpm off standby voltage regulator standby optionally on 6 6 voltage regulator will be on if bdm is enabled or if lvd is enabled when entering stop3. xosc off optionally on 7 7 erclken and erefsten set in icsc2, else in standby. for high frequency range (range in icsc2 set) requires the lvd to also be enabled in stop3. i/o pins states held states held
chapter 3 modes of operation mc9s08sh8 mcu series data sheet, rev. 1 36 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 37 chapter 4 memory 4.1 mc9s08sh8 memory map as shown in figure 4-1 , on-chip memory in the mc9s08sh8 series of mcus consists of ram, flash program memory for nonvolatile data storage, and i/o and control/status registers. the registers are divided into three groups: direct-page registers (0x0000 through 0x007f) high-page registers (0x1800 through 0x185f) nonvolatile registers (0xffb0 through 0xffbf) figure 4-1. mc9s08sh8 memory map direct page registers ram high page registers 512 bytes 0x0000 0x007f 0x0080 0x027f 0x1800 0x17ff 0x185f 0xffff 0x0280 mc9s08sh8 flash 8192 bytes 0x1860 MC9S08SH4 unimplemented 51,104 bytes 0xe000 0xdfff direct page registers ram high page registers 256 bytes 0x0000 0x007f 0x0080 0x1800 0x17ff 0x185f 0xffff flash 4096 bytes 0x1860 0x017f 0x0180 0xf000 0xefff unimplemented 5504 bytes 0x027f 0x0280 unimplemented 5504 bytes reserved 256 bytes unimplemented 51,104 bytes 0xe000 0xdfff reserved 4096 bytes
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 38 freescale semiconductor 4.2 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. the vector names shown in this table are the labels used in the freescale semiconductor provided equate file for the mc9s08sh8. table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:0xffc1 reserved 0xffc2:0xffc3 acmp vacmp 0xffc4:0xffc5 reserved 0xffc6:0xffc7 reserved 0xffc8:0xffc9 reserved 0xffca:0xffcb mtim over?w vmtim 0xffcc:0xffcd rtc vrtc 0xffce:0xffcf iic viic 0xffd0:0xffd1 adc conversion vadc 0xffd2:0xffd3 reserved 0xffd4:0xffd5 port b pin interrupt vportb 0xffd6:0xffd7 port a pin interrupt vporta 0xffd8:0xffd9 reserved 0xffda:0xffdb sci transmit vscitx 0xffdc:0xffdd sci receive vscirx 0xffde:0xffdf sci error vscierr 0xffe0:0xffe1 spi vspi 0xffe2:0xffe3 tpm2 over?w vtpm2ovf 0xffe4:0xffe5 tpm2 channel 1 vtpm2ch1 0xffe6:0xffe7 tpm2 channel 0 vtpm2ch0 0xffe8:0xffe9 tpm1 over?w vtpm1ovf 0xffea:0xffeb reserved 0xffec:0xffed reserved 0xffee:0xffef reserved 0xfff0:0xfff1 reserved 0xfff2:0xfff3 tpm1 channel 1 vtpm1ch1 0xfff4:0xfff5 tpm1 channel 0 vtpm1ch0 0xfff6:0xfff7 reserved 0xfff8:0xfff9 low voltage detect vlvd 0xfffa:0xfffb irq virq 0xfffc:0xfffd swi vswi 0xfffe:0xffff reset vreset
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 39 4.3 register addresses and bit assignments the registers in the mc9s08sh8 are divided into these groups: direct-page registers are located in the ?st 128 locations in the memory map; these are accessible with ef?ient direct addressing mode instructions. high-page registers are used much less often, so they are located above 0x1800 in the memory map. this leaves more room in the direct page for more frequently used registers and ram. the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?xffbf. nonvolatile register locations include: nvprot and nvopt are loaded into working registers at reset an 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with ef?ient direct addressing mode instructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page registers and control bits. the direct page registers in table 4-2 can use the more ef?ient direct addressing mode, which requires only the lower byte of the address. because of this, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-4 , the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 40 freescale semiconductor table 4-2. direct-page register summary (sheet 1 of 3) address register name bit 7 654321 bit 0 0x00 00 ptad 0 0 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 0x00 01 ptadd 0 0 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 0x00 02 ptbd ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 0x00 03 ptbdd ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 04 ptcd 0 0 0 0 ptcd3 ptcd2 ptcd1 ptcd0 0x00 05 ptcdd 0 0 0 0 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x0006 0x000d reserved 0x00 0e acmpsc acme acbgs acf acie aco acope acmod1 acmod0 0x000f reserved 0x00 10 adsc1 coco aien adco adch 0x00 11 adsc2 adact adtrg acfe acfgt 0x00 12 adrh 0 0 0 0 0 0 adr9 adr8 0x00 13 adrl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adcvh 0 0 0 0 0 0 adcv9 adcv8 0x00 15 adcvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adcfg adlpc adiv adlsmp mode adiclk 0x00 17 apctl1 adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 0x00 18 apctl2 0 0 0 0 adpc11 adpc10 adpc9 adpc8 0x0019 reserved 0x00 1a irqsc 0 irqpdd irqedg irqpe irqf irqack irqie irqmod 0x001b reserved 0x00 1c mtimsc tof toie trst tstp 0 0 0 0 0x00 1d mtimclk 0 0 clks ps 0x00 1e mtimcnt cnt 0x00 1f mtimmod mod 0x00 20 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm1cntl bit 7 654321 bit 0 0x00 23 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm1modl bit 7 654321 bit 0 0x00 25 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm1c0vl bit 7 654321 bit 0 0x00 28 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 29 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 2a tpm1c1vl bit 7 654321 bit 0 0x002b 0x0037 reserved
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 41 0x00 38 scibdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 39 scibdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 3a scic1 loops sciswai rsrc m wake ilt pe pt 0x00 3b scic2 tie tcie rie ilie te re rwu sbk 0x00 3c scis1 tdre tc rdrf idle or nf fe pf 0x00 3d scis2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 3e scic3 r8 t8 txdir txinv orie neie feie peie 0x00 3f scid bit 7 654321 bit 0 0x0040 0x0047 reserved 0x00 48 icsc1 clks rdiv irefs irclken irefsten 0x00 49 icsc2 bdiv range hgo lp erefs erclken erefsten 0x00 4a icstrm trim 0x00 4b icssc 0 0 0 irefst clkst oscinit ftrim 0x004c 0x004f reserved 0x00 50 spic1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 51 spic2 0 0 0 modfen bidiroe 0 spiswai spc0 0x00 52 spibr 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 53 spis sprf 0 sptef modf 0 0 0 0 0x0054 reserved 0 0 0 0 0 0 0 0 0x00 55 spid bit 7 654321 bit 0 0x0056 0x0057 reserved 0x00 58 iica ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 0x00 59 iicf mult icr 0x00 5a iicc1 iicen iicie mst tx txak rsta 0 0 0x00 5b iics tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iicd data 0x00 5d iicc2 gcaen adext 0 0 0 ad10 ad9 ad8 0x005e 0x005f reserved 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl bit 7 654321 bit 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl bit 7 654321 bit 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl bit 7 654321 bit 0 table 4-2. direct-page register summary (sheet 2 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 42 freescale semiconductor 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl bit 7 654321 bit 0 0x006b reserved 0x00 6c rtcsc rtif rtclks rtie rtcps 0x00 6d rtccnt rtccnt 0x00 6e rtcmod rtcmod 0x006f - 0x007f reserved table 4-2. direct-page register summary (sheet 3 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 43 high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. table 4-3. high-page register summary (sheet 1 of 2) address register name bit 7 654321 bit 0 0x1800 srs por pin cop ilop ilad 0lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0 bdfr 0x1802 sopt1 copt stope 0 0 iicps bkgdpe rstpe 0x1803 sopt2 copclks copw 0 acic 0 0 t1ch1ps t1ch0ps 0x1804 0x1805 reserved 0x1806 sdidh 0 id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 reserved 0x1809 spmsc1 lvwf lvwack lvwie lvdre lvdse lvde 0 bgbe 0x180a spmsc2 0 0 lvdv lvwv ppdf ppdack ppdc 0x180b 0x180f reserved 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7 654321 bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7 654321 bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7 654321 bit 0 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819 0x181f reserved 0x1820 fcdiv divld prdiv8 div 0x1821 fopt keyen fnored 0 0 0 0 sec 0x1822 reserved 0x1823 fcnfg 0 0 keyacc 0 0 0 0 0 0x1824 fprot fps fpdis 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd 0x1827 0x183f reserved 0x1840 ptape 0 0 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 0x1841 ptase 0 0 ptase4 ptase3 ptase2 ptase1 ptase0 0x1842 ptads 0 0 ptads4 ptads3 ptads2 ptads1 ptads0 0x1843 reserved 0x1844 ptasc 0 0 0 0 ptaif ptaack ptaie ptamod
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 44 freescale semiconductor 0x1845 ptaps 0 0 0 ptaps4 ptaps3 ptaps2 ptaps1 ptaps0 0x1846 ptaes 0 0 0 ptaes4 ptaes3 ptaes2 ptaes1 ptaes0 0x1847 reserved 0x1848 ptbpe ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x1849 ptbse ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 0x184a ptbds ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 0x184b reserved 0x184c ptbsc 0 0 0 0 ptbif ptback ptbie ptbmod 0x184d ptbps 0 0 0 0 ptbps3 ptbps2 ptbps1 ptbps0 0x184e ptbes 0 0 0 0 ptbes3 ptbes2 ptbes1 ptbes0 0x184f reserved 0x1850 ptcpe 0 0 0 0 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x1851 ptcse 0 0 0 0 ptcse3 ptcse2 ptcse1 ptcse0 0x1852 ptcds 0 0 0 0 ptcds3 ptcds2 ptcds1 ptcds0 0x1853 gngc gngps7 gngps6 gngps5 gngps4 gngps3 gngps2 gngps1 gngen 0x1854 0x185f reserved table 4-3. high-page register summary (sheet 2 of 2) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 45 nonvolatile flash registers, shown in table 4-4 , are located in the flash memory. these registers include an 8-byte backdoor key, nvbackkey, which can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt working registers in the high-page registers to control security and block protection options. provided the key enable (keyen) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. this key mechanism can be accessed only through user code running in secure memory. (a security key cannot be entered directly through background debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. to avoid returning to secure mode after the next reset, program the security bits (sec) to the unsecured state (1:0). table 4-4. nonvolatile register summary address register name bit 7 654321 bit 0 0xffae reserved for storage of ftrim 0 0 0 0 0 0 0 ftrim 0xffaf reserved for storage of icstrim trim 0xffb0 0xffb7 nvbackkey 8-byte comparison key 0xffb8 0xffbc reserved 0xffbd nvprot fps fpdis 0xffbe reserved 0xffbf nvopt keyen fnored 0 0 0 0 sec
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 46 freescale semiconductor 4.4 ram the mc9s08sh8 includes static ram. the locations in ram below 0x0100 can be accessed using the more ef?ient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or stop3 mode. at power-on the contents of ram are uninitialized. ram data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for ram retention (v ram ). for compatibility with m68hc05 mcus, the hcs08 resets the stack pointer to 0x00ff. in the mc9s08sh8, it is usually best to reinitialize the stack pointer to the top of the ram so the direct page ram can be used for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is equated to the highest address of the ram in the freescale semiconductor-provided equate ?e). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource and is not accessible through bdm or through code executing from non-secure memory. see section 4.6, ?ecurity? for a detailed description of the security feature. 4.5 flash the flash memory is intended primarily for program storage. in-circuit programming allows the operating program to be loaded into the flash memory after ?al assembly of the application product. it is possible to program the entire array through the single-wire background debug interface. because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. for a more detailed discussion of in-circuit and in-application programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor document order number hcs08rmv1/d.
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 47 4.5.1 features features of the flash memory include: flash size mc9s08sh8: 8,192 bytes (16 pages of 512 bytes each) MC9S08SH4: 4,096 bytes (8 pages of 512 bytes each) single power supply program and erase command interface for fast program and erase operation up to 100,000 program/erase cycles at typical voltage and temperature flexible block protection security feature for flash and ram auto power-down for low-frequency read accesses 4.5.2 program and erase times before any program or erase command can be accepted, the flash clock divider register (fcdiv) must be written to set the internal clock for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see section 4.7.1, ?lash clock divider register (fcdiv) ?. this register can be written only once, so normally this write is done during reset initialization. fcdiv cannot be written if the access error ?g, faccerr in fstat, is set. the user must ensure that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of these timing pulses are used by the command processor to complete a program or erase command. table 4-5 shows program and erase times. the bus clock frequency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk = 1/f fclk . the times are shown as a number of cycles of fclk and as an absolute time for the case where t fclk =5s. program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s 1 1 excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 48 freescale semiconductor 4.5.3 program and erase command execution the steps for executing any of the commands are listed below. the fcdiv register must be initialized and any error ?gs cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash array. the address and data information from this write is latched into the flash interface. this write is a required ?st step in any command sequence. for erase and blank check commands, the value of the data is not important. for page erase commands, the address may be any address in the 512-byte page of flash to be erased. for mass erase and blank check commands, the address can be any address in the flash memory. whole pages of 512 bytes are the smallest block of flash that may be erased. note do not program any byte in the flash more than once after a successful erase operation. reprogramming bits to a byte that is already programmed is not allowed without ?st erasing the page in which the byte resides or mass erasing the entire flash memory. programming without ?st erasing may disturb data stored in the flash. 2. write the command code for the desired command to fcmd. the ve valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr access error ?g, which must be cleared before starting a new command. a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended changes to the flash memory contents. the command complete ?g (fccf) indicates when a command is complete. the command sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a ?wchart for executing all of the commands except for burst programming. the fcdiv register must be initialized before using any flash commands. this must be done only once following a reset.
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 49 figure 4-2. flash program and erase flowchart 4.5.4 burst program execution the burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. this is possible because the high voltage to the flash array does not need to be disabled between program operations. ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the command, the charge pump is turned off. when a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met: the next burst program command has been queued before the current program operation has completed. the next sequential address selects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins when addresses a5 through a0 are all zero. start write to flash to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (note 2) 1 0 fccf ? error exit done note 2: wait at least four bus cycles 0 faccerr ? clear error faccerr ? write to fcdiv (note 1) note 1: required only once after reset. 1 before checking fcbef or fccf. flash program and erase flow
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 50 freescale semiconductor the ?st byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. subsequent bytes will program in the burst program time provided that the conditions above are met. in the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. figure 4-3. flash burst program flowchart 1 0 fcbef ? start write to flash to buffer address and data write command (0x25) to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef (note 2) no yes new burst command ? 1 0 fccf ? error exit done note 2: wait at least four bus cycles before 1 0 faccerr ? clear error faccerr ? note 1: required only once after reset. write to fcdiv (note 1) checking fcbef or fccf. flash burst program flow
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 51 4.5.5 access errors an access error occurs whenever the command execution protocol is violated. any of the following speci? actions will cause the access error ?g (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. writing to a flash address before the internal flash clock frequency has been set by writing to the fcdiv register writing to a flash address while fcbef is not set (a new command cannot be started until the command buffer is empty.) writing a second time to a flash address before launching the previous command (there is only one write to flash for every command.) writing a second time to fcmd before launching the previous command (there is only one write to fcmd for every command.) writing to any flash control register other than fcmd after writing to a flash address writing any command code other than the ve allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to fcmd writing any flash control register other than the write to fstat (to clear fcbef and launch the command) after writing the command to fcmd the mcu enters stop mode while a program or erase command is in progress (the command is aborted.) writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a background debug command while the mcu is secured (the background debug controller can only do blank check and mass erase commands when the mcu is secure.) writing 0 to fcbef to cancel a partial command 4.5.6 flash block protection the block protection feature prevents the protected region of flash from program or erase changes. block protection is controlled through the flash protection register (fprot). when enabled, block protection begins at any 512 byte boundary below the last address of flash, 0xffff. (see section 4.7.4, ?lash protection register (fprot and nvprot) ?. after exit from reset, fprot is loaded with the contents of the nvprot location, which is in the nonvolatile register block of the flash memory. fprot cannot be changed directly from application software so a runaway program cannot alter the block protection settings. because nvprot is within the last 512 bytes of flash, if any amount of memory is protected, nvprot is itself protected and cannot be altered (intentionally or unintentionally) by the application software. fprot can be written through background debug commands, which allows a way to erase and reprogram a protected flash memory. the block protection mechanism is illustrated in figure 4-4 . the fps bits are used as the upper bits of the last address of unprotected memory. this address is formed by concatenating fps7:fps1 with logic 1 bits as shown. for example, to protect the last 1536 bytes of memory (addresses 0xfa00 through 0xffff), the fps bits must be set to 1111 100, which results in the value 0xf9ff as the last address of unprotected memory. in addition to programming the fps bits to the appropriate value, fpdis (bit 0 of nvprot) must
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 52 freescale semiconductor be programmed to logic 0 to enable block protection. therefore the value 0xf8 must be programmed into nvprot to protect addresses 0xfa00 through 0xffff. figure 4-4. block protection mechanism one use for block protection is to block protect an area of flash memory for a bootloader program. this bootloader program then can be used to erase the rest of the flash memory and reprogram it. because the bootloader is protected, it remains intact even if mcu power is lost in the middle of an erase and reprogram operation. 4.5.7 vector redirection whenever any block protection is enabled, the reset and interrupt vectors will be protected. vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to zero. for redirection to occur, at least some portion but not all of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all of the interrupt vectors (memory locations 0xffc0?xfffd) are redirected, though the reset vector (0xfffe:ffff) is not. for example, if 512 bytes of flash are protected, the protected address region is from 0xfe00 through 0xffff. the interrupt vectors (0xffc0?xfffd) are redirected to the locations 0xfdc0?xfdfd. now, if an spi interrupt is taken for instance, the values in the locations 0xfde0:fde1 are used for the vector instead of the values in the locations 0xffe0:ffe1. this allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.6 security the mc9s08sh8 includes circuitry to prevent unauthorized access to the contents of flash and ram memory. when security is engaged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the state of two nonvolatile register bits (sec01:sec00) in the fopt register. during reset, the contents of the nonvolatile location nvopt are copied from flash into the working fopt register in high-page register space. a user engages security by programming the nvopt location which can be done at the same time the flash memory is programmed. the 1:0 state disengages security and the other three combinations engage security. notice the erased state (1:1) makes fps7 fps6 fps5 fps4 fps3 fps2 fps1 a15 a14 a13 a12 a11 a10 a9 a8 1 a7 a6 a5 a4 a3 a2 a1 a0 111 11111
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 53 the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec00 bit to 0 in nvopt so sec01:sec00 = 1:0. this would allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can still be used for background memory access commands of unsecured resources. a user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile keyen bit in nvopt/fopt is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporarily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbackkey+7) as values to be compared against the key rather than as the ?st step in a flash program or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be done in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx should not be used for these writes because these writes cannot be done on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication interface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was just written matches the key stored in the flash locations, sec01:sec00 are automatically changed to 1:0 and security will be disengaged until the next reset. the security key can be written only from secure memory (either ram or flash), so it cannot be entered through background commands without the cooperation of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other flash memory location. the nonvolatile registers are in the same 512-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through the background debug interface by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0. 4.7 flash registers and control bits the flash module has nine 8-bit registers in the high-page register space, two locations (nvopt, nvprot) in the nonvolatile register space in flash memory are copied into corresponding high-page
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 54 freescale semiconductor control registers (fopt, fprot) at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all flash registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses. 4.7.1 flash clock divider register (fcdiv) bit 7 of this register is a read-only ?g. bits 6:0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. if prdiv8 = 0 ?f fclk = f bus (div + 1) eqn. 4-1 if prdiv8 = 1 ?f fclk = f bus (8 (div + 1)) eqn. 4-2 table 4-7 shows the appropriate values for prdiv8 and div for selected bus frequencies. 76543210 r divld prdiv8 div w reset 00000000 = unimplemented or reserved figure 4-5. flash clock divider register (fcdiv) table 4-6. fcdiv register field descriptions field description 7 divld divisor loaded status flag when set, this read-only status ?g indicates that the fcdiv register has been written since reset. reset clears this bit and the ?st write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash. 1 fcdiv has been written since reset; erase and program operations enabled for flash. 6 prdiv8 prescale (divide) flash clock by 8 0 clock input to the flash clock divider is the bus rate clock. 1 clock input to the flash clock divider is the bus rate clock divided by 8. 5:0 div divisor for flash clock divider the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div ?ld plus one. the resulting frequency of the internal flash clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this internal flash clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 and equation 4-2 .
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 55 4.7.2 flash options register (fopt and nvopt) during reset, the contents of the nonvolatile location nvopt are copied from flash into fopt. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. table 4-7. flash clock divider settings f bus prdiv8 (binary) div (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s 76543210 r keyen fnored 0000 sec01 sec00 w reset this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-6. flash options register (fopt) table 4-8. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ?when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) ?mware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.6, ?ecurity . 0 no backdoor key access allowed. 1 if user ?mware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is temporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ?when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 1:0 sec0[1:0] security state code this 2-bit ?ld determines the security state of the mcu as shown in table 4-9 . when the mcu is secure, the contents of ram and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. for more detailed information about security, refer to section 4.6, ?ecurity .
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 56 freescale semiconductor 4.7.3 flash con?uration register (fcnfg) 4.7.4 flash protection register (fprot and nvprot) during reset, the contents of the nonvolatile location nvprot is copied from flash into fprot. this register can be read at any time. if fpdis = 0, protection can be increased (that is, a smaller value of fps can be written). if fpdis = 1, writes do not change protection. figure 4-8. flash protection register (fprot) table 4-9. security states 1 1 sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. sec01:sec00 description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 76543210 r0 0 keyacc 00000 w reset 00000000 = unimplemented or reserved figure 4-7. flash con?uration register (fcnfg) table 4-10. fcnfg register field descriptions field description 5 keyacc enable writing of access key ?this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.6, ?ecurity . 0 writes to 0xffb0?xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?xffb7) are interpreted as comparison key writes. 76543210 r fps (1) 1 background commands can be used to change the contents of these bits in fprot. fpdis (1) w reset this register is loaded from nonvolatile location nvprot during reset.
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 57 4.7.5 flash status register (fstat) table 4-11. fprot register field descriptions field description 7:1 fps flash protect select bits when fpdis = 0, this 7-bit ?ld determines the ending address of unprotected flash locations at the high address end of the flash. protected flash locations cannot be erased or programmed. 0 fpdis flash protection disable 0 flash block speci?d by fps[7:1] is block protected (program and erase not allowed). 1 no flash block is protected. 76543210 r fcbef fccf fpviol faccerr 0 fblank 0 0 w reset 11000000 = unimplemented or reserved figure 4-9. flash status register (fstat) table 4-12. fstat register field descriptions field description 7 fcbef flash command buffer empty flag the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command can be written to the command buffer. 6 fccf flash command complete flag ?fccf is set automatically when the command buffer is empty and no command is being processed. fccf is cleared automatically when a new command is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag fpviol is set automatically when a command is written that attempts to erase or program a location in a protected block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location.
chapter 4 memory mc9s08sh8 mcu series data sheet, rev. 1 58 freescale semiconductor 4.7.6 flash command register (fcmd) only ve command codes are recognized in normal user modes as shown in table 4-13 . refer to section 4.5.3, ?rogram and erase command execution ,?for a detailed discussion of flash programming and erase operations. all other command codes are illegal and generate an access error. it is not necessary to perform a blank check command after a mass erase operation. only blank check is required as part of the security unlocking mechanism. 4 faccerr access error flag faccerr is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the fcdiv register has been initialized, or if the mcu enters stop while a command was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.5.5, ?ccess errors . faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank flash veri?d as all blank (erased) flag fblank is set automatically at the conclusion of a blank check command if the entire flash array was veri?d to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all 0xff). 76543210 r00000000 w fcmd reset 00000000 figure 4-10. flash command register (fcmd) table 4-13. flash commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog byte program ?burst mode 0x25 mburstprog page erase (512 bytes/page) 0x40 mpageerase mass erase (all flash) 0x41 mmasserase table 4-12. fstat register field descriptions (continued) field description
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 59 chapter 5 resets, interrupts, and general system control 5.1 introduction this section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the mc9s08sh8. some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. this section gathers basic information about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog are not part of on-chip peripheral systems with their own chapters. 5.2 features reset and interrupt features include: multiple sources of reset for ?xible system con?uration and reliable operation reset status register (srs) to indicate source of most recent reset separate interrupt vector for each module (reduces polling overhead) (see table 5-2 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral modules are disabled and i/o pins are initially con?ured as general-purpose high-impedance inputs with pull-up devices disabled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system control settings. sp is forced to 0x00ff at reset. the mc9s08sh8 has the following sources for reset: power-on reset (por) external pin reset (pin) - enabled using rstpe in sopt1 low-voltage detect (lvd) computer operating properly (cop) timer illegal opcode detect (ilop) illegal address detect (ilad) background debug forced reset each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (srs).
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 60 freescale semiconductor 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset when the application software fails to execute as expected. to prevent a system reset from the cop timer (when it is enabled), application software must reset the cop counter periodically. if the application program gets lost and fails to reset the cop counter before it times out, a system reset is generated to force the system back to a known starting point. after any reset, the cop watchdog is enabled (see section 5.7.4, ?ystem options register 1 (sopt1) , for additional information). if the cop watchdog is not used in an application, it can be disabled by clearing copt bits in sopt1. the cop counter is reset by writing 0x0055 and 0x00aa (in this order) to the address of srs during the selected timeout period. writes do not affect the data in the read-only srs. as soon as the write sequence is done, the cop timeout period is restarted. if the program fails to do this during the time-out period, the mcu will reset. also, if any value other than 0x0055 or 0x00aa is written to srs, the mcu is immediately reset. the copclks bit in sopt2 (see section 5.7.5, ?ystem options register 2 (sopt2) ,?for additional information) selects the clock source used for the cop timer. the clock source options are either the bus clock or an internal 1-khz clock source. with each clock source, there are three associated time-outs controlled by the copt bits in sopt1. table 5-1 summaries the control functions of the copclks and copt bits. the cop watchdog defaults to operation from the 1-khz clock source and the longest time-out (2 10 cycles). table 5-1. cop con?uration options when the bus clock source is selected, windowed cop operation is available by setting copw in the sopt2 register. in this mode, writes to the srs register to clear the cop timer must occur in the last 25% of the selected timeout period. a premature write immediately resets the mcu. when the 1-khz clock source is selected, windowed cop operation is not available. control bits clock source cop window 1 opens (copw = 1) 1 windowed cop operation requires the user to clear the cop timer in the last 25% of the selected timeout period. this column displays the minimun number of clock counts required before the cop timer can be reset hen in windowed cop mode (copw = 1). cop over?w count copclks copt[1:0] n/a 0:0 n/a n/a cop is disabled 0 0:1 1 khz n/a 2 5 cycles (32 ms 2 ) 2 values shown in in miliseconds based on t lpo = 1 ms. see t lpo in the appendix section a.12.1, ?ontrol timing ?for the tolerance of this value. 0 1:0 1 khz n/a 2 8 cycles (256 ms 1 ) 0 1:1 1 khz n/a 2 10 cycles (1.024 s 1 ) 1 0:1 bus 6144 cycles 2 13 cycles 1 1:0 bus 49,152 cycles 2 16 cycles 1 1:1 bus 196,608 cycles 2 18 cycles
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 61 the cop counter is initialized by the ?st writes to the sopt1 and sopt2 registers after any system reset. subsequent writes to sopt1 and sopt2 have no effect on cop operation. even if the application will use the reset default settings of copt, copclks, and copw bits, the user should write to the write-once sopt1 and sopt2 registers during reset initialization to lock in the settings. this will prevent accidental changes if the application program gets lost. the write to srs that services (clears) the cop counter should not be placed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. if the bus clock source is selected, the cop counter does not increment while the mcu is in background debug mode or while the system is in stop mode. the cop counter resumes when the mcu exits background debug mode or stop mode. if the 1-khz clock source is selected, the cop counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode. 5.5 interrupts interrupts provide a way to save the current cpu status and registers, execute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caused by hardware events such as an edge on the irq pin or a timer-over?w event. the debug module can also generate an swi under certain circumstances. if an event occurs in an enabled interrupt source, an associated read-only status ?g will become set. the cpu will not respond unless the local interrupt enable is a 1 to enable the interrupt and the i bit in the ccr is 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which prevents all maskable interrupt sources. the user program initializes the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a quali?d interrupt request, it completes the current instruction before responding to the interrupt. the interrupt sequence obeys the same cycle-by-cycle sequence as the swi instruction and consists of: saving the cpu registers on the stack setting the i bit in the ccr to mask further interrupts fetching the interrupt vector for the highest-priority interrupt that is currently pending filling the instruction queue with the ?st three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restored from the value stacked on entry to the isr. in rare cases, the i bit can be cleared inside an isr (after clearing the status ?g that generated the interrupt) so that other interrupts can be serviced without waiting for the ?st service routine to ?ish. this practice is not recommended for anyone
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 62 freescale semiconductor other than the most experienced programmers because it can lead to subtle program errors that are dif?ult to debug. the interrupt service routine ends with a return-from-interrupt (rti) instruction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information from the stack. note for compatibility with m68hc08 devices, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service routine (isr) and restore it immediately before the rti that is used to return from the isr. if more than one interrupt is pending when the i bit is cleared, the highest priority source is serviced ?st (see table 5-2 ). 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next available byte location on the stack. the current values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next available location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu ?ls the instruction pipeline by reading three bytes of program information, starting from the pc address recovered from the stack. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index register is not automatically stacked. * program counter low 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 63 the status ?g corresponding to the interrupt source must be acknowledged (cleared) before returning from the isr. typically, the ?g is cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current isr. 5.5.2 external interrupt request pin (irq) external interrupts are managed by the irq status and control register, irqsc. when the irq function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 pin con?uration options the irq pin enable (irqpe) control bit in irqsc must be 1 in order for the irq pin to act as the interrupt request (irq) input. as an irq input, the user can choose the polarity of edges or levels detected (irqedg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or only sets the irqf ?g which can be polled by software. the irq pin, when enabled, defaults to use an internal pull device (irqpdd = 0), the device is a pull-up or pull-down depending on the polarity chosen. if the user desires to use an external pull-up or pull-down, the irqpdd can be written to a 1 to turn off the internal device. bih and bil instructions may be used to detect the level on the irq pin when the pin is con?ured to act as the irq input. note this pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up irq pin will not be pulled to v dd . the internal gates connected to this pin are pulled to v dd . if the irq pin is required to drive to a v dd level an external pullup should be used. 5.5.2.2 edge and level sensitivity the irqmod control bit recon?ures the detection logic so it detects edge events and pin levels. in the edge and level detection mode, the irqf status ?g becomes set when an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the ?g is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-2 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byte of the address for the interrupt service routine is located at the ?st address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 64 freescale semiconductor when an interrupt condition occurs, an associated ?g bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will ?ish the current instruction; stack the pcl, pch, x, a, and ccr cpu registers; set the i bit; and then fetch the interrupt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine. table 5-2. vector summary vector priority vector number address (high/low) vector name module source enable description lowest highest 31 0xffc0/0xffc1 30 0xffc2/0xffc3 vacmp acmp acf acie analog comparator 29 0xffc4/0xffc5 28 0xffc6/0xffc7 27 0xffc8/0xffc9 26 0xffca/0xffcb vmtim mtim tof toie mtim over?w 25 0xffcc/0xffcd vrtc rtc rtif rtie real-time interrupt 24 0xffce/0xffcf viic iic iicif iicie iic control 23 0xffd0/0xffd1 vadc adc coco aien adc 22 0xffd2/0xffd3 21 0xffd4/0xffd5 vportb port b ptbif ptbie port b pins 20 0xffd6/0xffd7 vporta port a ptaif ptaie port a pins 19 0xffd8/0xffd9 18 0xffda/0xffdb vscitx sci tdre, tc tie, tcie sci transmit 17 0xffdc/0xffdd vscirx sci idle, rdrf, lbkdie, rxedgie ilie, rie, ldbkdif, rxedge sci receive 16 0xffde/0xffdf vscierr sci or, nf, fe, pf orie, nfie, feie, pfie sci error 15 0xffe0/0xffe1 vspi spi spif, modf, sptef spie, spie, sptie spi 14 0xffe2/0xffe3 vtpm2ovf tpm2 tof toie tpm2 over?w 13 0xffe4/0xffe5 vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 12 0xffe6/0xffe7 vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 11 0xffe8/0xffe9 vtpm1ovf tpm1 tof toie tpm1 over?w 10 0xffea/0xffeb 9 0xffec/0xffed 8 0xffee/0xffef 7 0xfff0/0xfff1 6 0xfff2/0xfff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4/0xfff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6/0xfff7 3 0xfff8/0xfff9 vlvd system control lvwf lvwie low-voltage warning 2 0xfffa/0xfffb virq irq irqf irqie irq pin 1 0xfffc/0xfffd vswi core swi instruction software interrupt 0 0xfffe/0xffff vreset system control cop, lv d, reset pin, illegal opcode, illegal address copt lvdre watchdog timer low-voltage detect external pin illegal opcode illegal address
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 65 5.6 low-voltage detect (lvd) system the mc9s08sh8 includes a system to protect against low voltage conditions in order to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and a lvd circuit with trip voltages for warning and detection. the lvd circuit is enabled when lvde in spmsc1 is set to 1. the lvd is disabled upon entering any of the stop modes unless lvdse is set in spmsc1. if lvdse and lvde are both set, then the mcu cannot enter stop2, and the current consumption in stop3 with the lvd enabled will be higher. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the power-on reset rearm voltage level, v por , the por circuit will cause a reset condition. as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above the low voltage detection low threshold, v lvdl . both the por bit and the lvd bit in srs are set following a por. 5.6.2 low-voltage detection (lvd) reset operation the lvd can be con?ured to generate a reset upon detection of a low voltage condition by setting lvdre to 1. the low voltage detection threshold is determined by the lvdv bit. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the low voltage detection threshold. the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 low-voltage warning (lvw) interrupt operation the lvd system has a low voltage warning ?g to indicate to the user that the supply voltage is approaching the low voltage condition. when a low voltage warning condition is detected and is con?ured for interrupt operation (lvwie set to 1), lvwf in spmsc1 will be set and an lvw interrupt request will occur. 5.7 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. refer to table 4-2 and table 4-3 in chapter 4, ?emory ,?of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. some control bits in the sopt1 and spmsc2 registers are related to modes of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?odes of operation .
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 66 freescale semiconductor 5.7.1 interrupt pin request status and control register (irqsc) this direct page register includes status and control bits, which are used to con?ure the irq function, report status, and acknowledge irq events. 76543210 r0 irqpdd irqedg irqpe irqf 0 irqie irqmod w irqack reset 00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc) table 5-3. irqsc register field descriptions field description 6 irqpdd interrupt request (irq) pull device disable this read/write control bit is used to disable the internal pullup device when the irq pin is enabled (irqpe = 1) allowing for an external device to be used. 0 irq pull device enabled if irqpe = 1. 1 irq pull device disabled if irqpe = 1. 5 irqedg interrupt request (irq) edge select ?this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the irq pin is enabled as the irq input and is con?ured to detect rising edges. when irqedg = 1 and the internal pull device is enabled, the pull-up device is recon?ured as an optional pull-down device. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable this read/write control bit enables the irq pin function. when this bit is set the irq pin can be used as an interrupt request. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ?this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 2 irqack irq acknowledge this write-only bit is used to acknowledge interrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detection is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ?this read/write control bit determines whether irq events generate an interrupt request. 0 interrupt request when irqf set is disabled (use polling). 1 interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ?this read/write control bit selects either edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see section 5.5.2.2, ?dge and level sensitivity ,?for more details. 0 irq event on falling edges or rising edges only. 1 irq event on falling edges and low levels or on rising edges and high levels.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 67 5.7.2 system reset status register (srs) this high page register includes read-only status ?gs to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdfr register, none of the status bits in srs will be set. writing any value to this register address causes a cop reset when the cop is enabled except the values 0x55 and 0xaa. writing a 0x55-0xaa sequence to this address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset. figure 5-3. system reset status (srs) 76543210 r por pin cop ilop ilad 0 lvd 0 w writing 0x55, 0xaa to srs address clears cop watchdog timer. por: 10000010 lvr: u (1) 1 u = unaffected 0000010 any other reset: 0 note (2) 2 any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. note (2) note (2) note (2) 000 table 5-4. srs register field descriptions field description 7 por power-on reset reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ?reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog reset was caused by the cop watchdog timer timing out. this reset source can be blocked by copt bits = 0:0.. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode reset was caused by an attempt to execute an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt register. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 68 freescale semiconductor 5.7.3 system background debug force reset register (sbdfr) this high page register contains a single write-only control bit. a serial background command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. figure 5-4. system background debug force reset register (sbdfr) 3 ilad illegal address reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 reset not caused by an illegal address 1 reset caused by an illegal address 1 lv d low voltage detect if the lvdre bit is set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background debug commands, not from user programs. reset: 00000000 = unimplemented or reserved table 5-5. sbdfr register field descriptions field description 0 bdfr background debug force reset a serial background command such as write_byte can be used to allow an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program. table 5-4. srs register field descriptions field description
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 69 5.7.4 system options register 1 (sopt1) this high page register is a write-once register so only the ?st write after reset is honored. it can be read at any time. any subsequent attempt to write to sopt1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt1 should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 7654 1 1 bit 4 is reserved, writes change the value, but will have no effect on this mcu. 3210 r copt stope 0 iicps bkgdpe rstpe w reset: 1100001u 2 2 u = unaffected por: 11000010 lvr: 1100001u = unimplemented or reserved figure 5-5. system options register 1 (sopt1) table 5-6. sopt1 register field descriptions field description 7:6 copt[1:0] cop watchdog timeout ?these write-once bits select the timeout period of the cop. copt along with copclks in sopt2 de?es the cop timeout period. see table 5-1 . 5 stope stop mode enable ?this write-once bit is used to enable stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled. 2 iicps iic pin select ?this bit selects the location of the sda and scl pins of the iic module. 0 sda on pta2, scl on pta3. 1 sda on ptb6, scl on ptb7. 1 bkgdpe background debug mode pin enable ?this write-once bit when set enables the pta4/acmpo/bkgd/ms pin to function as bkgd/ms. when clear, the pin functions as one of its output-only alternative functions. this pin defaults to the bkgd/ms function following any mcu reset. 0 pta4/acmpo/bkgd/ms pin functions as pta4 or acmpo. 1 pta4/acmpo/bkgd/ms pin functions as bkgd/ms. 0 rstpe reset pin enable ?this write-once bit when set enables the pta5/irq/tclk/ reset pin to function as reset. when clear, the pin functions as one of its alternative functions. this pin defaults to a general-purpose input port function following a por reset. when con?ured as reset, the pin will be unaffected by lvr or other internal resets. when rstpe is set, an internal pullup device is enabled on reset. 0 pta5/irq/tclk/ reset pin functions as pta5, irq or tclk. 1 pta5/irq/tclk/ reset pin functions as reset.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 70 freescale semiconductor 5.7.5 system options register 2 (sopt2) this high page register contains bits to con?ure mcu speci? features on the mc9s08sh8 devices. 76543210 r copclks 1 1 this bit can be written only one time after reset. additional writes are ignored. copw 1 0 acic 00 t1ch1ps t1ch0ps w reset: 00000000 = unimplemented or reserved figure 5-6. system options register 2 (sopt2) table 5-7. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ?this write-once bit selects the clock source of the cop watchdog. 0 internal 1-khz clock is source to cop. 1 bus clock is source to cop. 6 copw cop window this write-once bit selects the cop operation mode. when set, the 0x55-0xaa write sequence to the srs register must occur in the last 25% of the selected period. any write to the srs register during the ?st 75% of the selected period will reset the mcu. 0 normal cop operation 1 window cop operation (only if copclks = 1) 4 acic analog comparator to input capture enable this bit connects the output of acmp to tpm1 input channel 0. 0 acmp output not connected to tpm1 input channel 0. 1 acmp output connected to tpm1 input channel 0. 1 t1ch1ps tpm1ch1 pin select ?this selects the location of the tpm1ch1 pin of the tpm1 module. 0 tpm1ch1 on ptb5. 1 tpm1ch1 on ptc1. 0 t1ch0ps tpm1ch0 pin select ?this bit selects the location of the tpm1ch0 pin of the tpm1 module. 0 tpm1ch0 on pta0. 1 tpm1ch0 on ptc0.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 71 5.7.6 system device identi?ation register (sdidh, sdidl) these high page read-only registers are included so host development systems can identify the hcs08 derivative and revision number. this allows the development software to recognize where speci? memory blocks, registers, and control bits are located in a target mcu. figure 5-7. system device identi?ation register ?high (sdidh) 76543210 r0 id11 id10 id9 id8 w reset: 0 1 1 - bit 7 is a mask option tie off that is used internally to determine that the device is a mc9s08sh8. 0000 = unimplemented or reserved table 5-8. sdidh register field descriptions field description 7 bit 7 will read as a 0 for the mc9s08sh8 devices; writes have no effect. 6:4 reserved bits 6:4 are reserved. reading these bits will result in an indeterminate value; writes have no effect. 3:0 id[11:8] part identi?ation number ?each derivative in the hcs08 family has a unique identi?ation number. the mc9s08sh8 is hard coded to the value 0x014. see also id bits in table 5-9 . 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w reset: 00010100 = unimplemented or reserved figure 5-8. system device identi?ation register ?low (sdidl) table 5-9. sdidl register field descriptions field description 7:0 id[7:0] part identi?ation number ?each derivative in the hcs08 family has a unique identi?ation number. the mc9s08sh8 is hard coded to the value 0x014. see also id bits in table 5-8 .
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 72 freescale semiconductor 5.7.7 system power management status and control 1 register (spmsc1) this high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the adc module. figure 5-9. system power management status and control 1 register (spmsc1) 76543210 r lvwf 1 1 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w 0 lvwie lvdre lvdse lvde 0 bgbe w lv wac k reset: 00011100 = unimplemented or reserved table 5-10. spmsc1 register field descriptions field description 7 lvwf low-voltage warning flag ?the lvwf bit indicates the low voltage warning status. 0 low voltage warning is not present. 1 low voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ?the lvwf bit indicates the low voltage warning status.writing a 1 to lvwack clears lvwf to a 0 if a low voltage warning is not present. 5 lvwie low-voltage warning interrupt enable ?this bit enables hardware interrupt requests for lvwf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvwf = 1. 4 lvdre low-voltage detect reset enable ?this write-once bit enables lvd events to generate a hardware reset (provided lvde = 1). 0 lvd events do not generate hardware resets. 1 force an mcu reset when an enabled low-voltage detect event occurs. 3 lvdse low-voltage detect stop enable ?provided lvde = 1, this control bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lvde low-voltage detect enable this write-once bit enables low-voltage detect logic and quali?s the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable this bit enables an internal buffer for the bandgap voltage reference for use by the adc module on one of its internal channels or acmp on its acmp+ input. 0 bandgap buffer disabled. 1 bandgap buffer enabled.
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 73 5.7.8 system power management status and control 2 register (spmsc2) this register is used to report the status of the low voltage warning function, and to con?ure the stop mode behavior of the mcu. figure 5-10. system power management status and control 2 register (spmsc2) 76543 210 r0 0 lv dv 1 1 this bit can be written only one time after power-on reset. additional writes are ignored. lvwv ppdf 0 0 ppdc 2 2 this bit can be written only one time after reset. additional writes are ignored. w ppdack power-on reset: 0 0 0 0 0 0 0 0 lvd reset: 0 0 u u 0 0 0 0 any other reset: 0 0 u u 0 0 0 0 = unimplemented or reserved u = unaffected by reset table 5-11. spmsc2 register field descriptions field description 5 lv dv low-voltage detect voltage select this write-once bit selects the low voltage detect (lvd) trip point setting. it also selects the warning voltage range. see table 5-12 . 4 lvwv low-voltage warning voltage select this bit selects the low voltage warning (lvw) trip point voltage. see table 5-12 . 3 ppdf partial power down flag ?this read-only status bit indicates that the mcu has recovered from stop2 mode. 0 mcu has not recovered from stop2 mode. 1 mcu recovered from stop2 mode. 2 ppdack partial power down acknowledge ?writing a 1 to ppdack clears the ppdf bit 0 ppdc partial power down control ?this write-once bit controls whether stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled. table 5-12. lvd and lvw trip point typical values 1 1 see electrical characteristics appendix for minimum and maximum values. lvdv:lvwv lvw trip point lvd trip point 0:0 v lvw0 = 2.74 v v lvd0 = 2.56 v 0:1 v lvw1 = 2.92 v 1:0 v lvw2 = 4.3 v v lvd1 = 4.0 v 1:1 v lvw3 = 4.6 v
chapter 5 resets, interrupts, and general system control mc9s08sh8 mcu series data sheet, rev. 1 74 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 75 chapter 6 parallel input/output control this section explains software controls related to parallel input/output (i/o) and pin control. the mc9s08sh8 has three parallel i/o ports which include a total of 17 i/o pins and one output-only pin. see chapter 2, ?ins and connections ,?for more information about pin assignments and external hardware considerations of these pins. many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or pin interrupts as shown in table 2-1 . the peripheral modules have priority over the general-purpose i/o functions so that when a peripheral is enabled, the i/o functions associated with the shared pins are disabled. after reset, the shared peripheral functions are disabled and the pins are con?ured as inputs (ptxddn = 0). the pin control functions for each pin are con?ured as follows: slew rate disabled (ptxsen = 0), low drive strength selected (ptxdsn = 0), and internal pull-ups disabled (ptxpen = 0). note not all general-purpose i/o pins are available on all packages. to avoid extra current drain from ?ating input pins, the users reset initialization routine in the application program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so the pins do not ?at. 6.1 port data and data direction reading and writing of parallel i/os are performed through the port data registers. the direction, either input or output, is controlled through the port data direction registers. the parallel i/o port function for an individual pin is illustrated in the block diagram shown in figure 6-1 . the data direction control bit (ptxddn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. the input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin. when a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. however, the data direction register bit will continue to control the source for reads of the port data register. when a shared analog function is enabled for a pin, both the input and output buffers are disabled. a value of 0 is read for any port data bit where the bit is an input (ptxddn = 0) and the input buffer is disabled. in general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 76 freescale semiconductor it is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. this ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. figure 6-1. parallel i/o block diagram 6.2 pull-up, slew rate, and drive strength associated with the parallel i/o ports is a set of registers located in the high page register space that operate independently of the parallel i/o registers. these registers are used to control pull-ups, slew rate, and drive strength for the pins. an internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up enable register (ptxpen). the pull-up device is disabled if the pin is con?ured as an output by the parallel i/o control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. the pull-up device is also disabled if the pin is controlled by an analog function. slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (ptxsen). when enabled, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins that are con?ured as inputs. an output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (ptxdsn). when high drive is selected, a pin is capable of sourcing and sinking greater current. even though every i/o pin can be selected as high drive, the user must ensure that the total current source and sink limits for the mcu are not exceeded. drive strength selection is intended to affect the dc behavior of i/o pins. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this, the emc emissions may be affected by enabling pins as high drive. q d q d 1 0 port read ptxddn ptxdn output enable output data input data synchronizer data busclk
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 77 6.3 ganged output the mc9s08sh8 devices contain a feature that allows for up to eight port pins to be tied together externally to allow higher output current drive. the ganged output drive control register (gngc) is a write-once register that is used to enabled the ganged output feature and select which port pins will be used as ganged outputs. the gngen bit in gngc enables ganged output. the gngps[7:1] bits are used to select which pin will be part of the ganged output. when gngen is set, any pin that is enabled as a ganged output will be automatically con?ured as an output and follow the data, drive strength and slew rate control of ptc0. the ganged output drive pin mapping is shown in table 6-1 . note see the dc characteristics in the electrical section for maximum port i/o currents allowed for this mcu. when a pin is enabled as ganged output, this feature will have priority over any digital module. an enabled analog function will have priority over the ganged output pin. see table 2-1 for information on pin priority. . table 6-1. ganged output pin enable gngc register bits gngps7 gngps6 gngps5 gngps4 gngps3 gngps2 gngps1 gngen 1 1 ganged output not available on 8-pin packages. ptc3-ptc0 not available on 16-pin packages, however ptc0 control registers are still used to control ganged output. port pin 2 2 when gngen = 1, ptc0 is forced to an output, regardless of the value in ptcdd0 in ptcdd. ptb5 ptb4 ptb3 ptb2 ptc3 ptc2 ptc1 ptc0 data direction control pin is automatically con?ured as output when pin is enabled as ganged output. data control ptcd0 in ptcd controls data value of output drive strength control ptcds0 in ptcds controls drive stength of output slew rate control ptcse0 in ptcse controls slew rate of output
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 78 freescale semiconductor 6.4 pin interrupts port a[3:0] and port b[3:0] pins can be con?ured as external interrupt inputs and as an external means of waking the mcu from stop3 or wait low-power modes. the block diagram for the pin interrupts is shown figure 6-2 . figure 6-2. pin interrupt block diagram writing to the ptxpsn bits in the port interrupt pin enable register (ptxps) independently enables or disables each port pin interrupt. each port can be con?ured as edge sensitive or edge and level sensitive based on the ptxmod bit in the port interrupt status and control register (ptxsc). edge sensitivity can be software programmed to be either falling or rising; the level can be either low or high. the polarity of the edge or edge and level sensitivity is selected using the ptxesn bits in the port interrupt edge select register (ptxes). synchronous logic is used to detect edges. prior to detecting an edge, enabled pin interrupt inputs must be at the deasserted logic level. a falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 6.4.1 edge only sensitivity a valid edge on an enabled pin interrupt will set ptxif in ptxsc. if ptxie in ptxsc is set, an interrupt request will be presented to the cpu. clearing of ptxif is accomplished by writing a 1 to ptxack in ptxsc. 6.4.2 edge and level sensitivity a valid edge or level on an enabled pin interrupt will set ptxif in ptxsc. if ptxie in ptxsc is set, an interrupt request will be presented to the cpu. clearing of ptxif is accomplished by writing a 1 to ptxack in ptxsc provided all enabled pin interrupt inputs are at their deasserted levels. ptxif will remain set if any enabled pin interrupt is asserted while attempting to clear by writing a 1 to ptxack. ptxesn dq ck clr v dd ptxmod ptxie port interrupt ff ptxack reset synchronizer ptxif stop bypass stop busclk ptxpsn 0 1 s ptxps0 0 1 s ptxes0 pixn pixn ptx interrupt request
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 79 6.4.3 pull-up/pull-down resistors the pin interrupts can be con?ured to use an internal pull-up/pull-down resistor using the associated i/o port pull-up enable register. if an internal resistor is enabled, the ptxes register is used to select whether the resistor is a pull-up (ptxesn = 0) or a pull-down (ptxesn = 1). 6.4.4 pin interrupt initialization when a pin interrupt is ?st enabled, it is possible to get a false interrupt ?g. to prevent a false interrupt request during pin interrupt initialization, the user should do the following: 1. mask interrupts by clearing ptxie in ptxsc. 2. select the pin polarity by setting the appropriate ptxesn bits in ptxes. 3. if using internal pull-up/pull-down device, con?ure the associated pull enable bits in ptxpe. 4. enable the interrupt pins by setting the appropriate ptxpsn bits in ptxps. 5. write to ptxack in ptxsc to clear any false interrupts. 6. set ptxie in ptxsc to enable interrupts. 6.5 pin behavior in stop modes pin behavior following execution of a stop instruction depends on the stop mode that is entered. an explanation of pin behavior for the various stop modes follows: stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was executed. cpu register status and the state of i/o registers should be saved in ram before the stop instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user should examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initialized as if a power on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals may require being initialized and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in the spmsc2 register. access to i/o is now permitted again in the user application program. in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user. 6.6 parallel i/o and pin control registers this section provides information about the registers associated with the parallel i/o ports. the data and data direction registers are located in page zero of the memory map. the pull up, slew rate, drive strength, and interrupt control registers are located in the high page section of the memory map. refer to tables in chapter 4, ?emory , for the absolute address assignments for all parallel i/o and their pin control registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 80 freescale semiconductor 6.6.1 port a registers port a is controlled by the registers listed below. the pins pta4 and pta5 are unique. pta4 is output-only, so the control bits for the input function will not have any effect on this pin. pta5, when con?ured as an output, is open drain with low drive strength. note this pta5 pin does not contain a clamp diode to v dd and should not be driven above v dd . when the internal pullup device is enabled on pta5 when used as an input or open drain output the voltage measured on pta5 will not be pulled to v dd . the internal gates connected to this pin are pulled to v dd . if the pta5 pin is required to drive to a v dd level an external pullup should be used. 6.6.1.1 port a data register (ptad) 76543210 r 00 ptad5 ptad4 1 1 reads of bit ptad4 always return the contents of ptad4, regardless of the value stored in bit ptadd4. ptad3 ptad2 ptad1 ptad0 w reset: 00000000 figure 6-3. port a data register (ptad) table 6-2. ptad register field descriptions field description 5:0 ptad[5:0] port a data register bits ?for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port a pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 81 6.6.1.2 port a data direction register (ptadd) 6.6.1.3 port a pull enable register (ptape) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 76543210 r 00 ptadd5 ptadd4 1 1 ptadd4 has no effect on the output-only pta4 pin. ptadd3 ptadd2 ptadd1 ptadd0 w reset: 00000000 figure 6-4. port a data direction register (ptadd) table 6-3. ptadd register field descriptions field description 5:0 ptadd[5:0] data direction for port a bits these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn. 76543210 r 00 ptape5 1 1 ptape5 can be used to pullup pta5 when con?ured as open drain output pin, however pullup will not pull pin all the way to v dd . an external pullup should be used if applications requires pta5 to be driven to v dd . ptape4 2 2 ptape4 has no effect on the output-only pta4 pin. ptape3 ptape2 ptape1 ptape0 w reset: 00000000 figure 6-5. internal pull enable for port a register (ptape) table 6-4. ptape register field descriptions field description 5:0 ptape[5:0] internal pull enable for port a bits each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated pta pin. for port a pins (except for pta5) that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port a bit n. 1 internal pull-up/pull-down device enabled for port a bit n.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 82 freescale semiconductor 6.6.1.4 port a slew rate enable register (ptase) 6.6.1.5 port a drive strength selection register (ptads) 76543210 r 00 r ptase4 ptase3 ptase2 ptase1 ptase0 w reset: 00000000 figure 6-6. slew rate enable for port a register (ptase) table 6-5. ptase register field descriptions field description 5 reserved reserved bits ?these bits are unused on this mcu, writes have no affect and could read as 1s or 0s. 4:0 ptase[4:0] output slew rate enable for port a bits each of these control bits determines if the output slew rate control is enabled for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n. 76543210 r 00 r ptads4 ptads3 ptads2 ptads1 ptads0 w reset: 00000000 figure 6-7. drive strength selection for port a register (ptads) table 6-6. ptads register field descriptions field description 5 reserved reserved bits ?these bits are unused on this mcu, writes have no affect and could read as 1s or 0s. 4:0 ptads[4:0] output drive strength selection for port a bits ?each of these control bits selects between low and high output drive for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port a bit n. 1 high output drive strength selected for port a bit n.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 83 6.6.1.6 port a interrupt status and control register (ptasc) 6.6.1.7 port a interrupt pin select register (ptaps) 76543210 r0000p t a i f0 ptaie ptamod w ptaack reset: 00000000 figure 6-8. port a interrupt status and control register (ptasc) table 6-7. ptasc register field descriptions field description 3 ptaif port a interrupt flag ?ptaif indicates when a port a interrupt is detected. writes have no effect on ptaif. 0 no port a interrupt detected. 1 port a interrupt detected. 2 ptaack port a interrupt acknowledge ?writing a 1 to ptaack is part of the ?g clearing mechanism. ptaack always reads as 0. 1 ptaie port a interrupt enable ?ptaie determines whether a port a interrupt is requested. 0 port a interrupt request not enabled. 1 port a interrupt request enabled. 0 ptamod port a detection mode ?ptamod (along with the ptaes bits) controls the detection mode of the port a interrupt pins. 0 port a pins detect edges only. 1 port a pins detect both edges and levels. 76543210 r0000 ptaps3 ptaps2 ptaps1 ptaps0 w reset: 00000000 figure 6-9. port a interrupt pin select register (ptaps) table 6-8. ptaps register field descriptions field description 3:0 ptaps[3:0] port a interrupt pin selects ?each of the ptapsn bits enable the corresponding port a interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 84 freescale semiconductor 6.6.1.8 port a interrupt edge select register (ptaes) 76543210 r0000 ptaes3 ptaes2 ptaes1 ptaes0 w reset: 00000000 figure 6-10. port a edge select register (ptaes) table 6-9. ptaes register field descriptions field description 3:0 ptaes[3:0] port a edge selects ?each of the ptaesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 85 6.6.2 port b registers port b is controlled by the registers listed below. 6.6.2.1 port b data register (ptbd) 6.6.2.2 port b data direction register (ptbdd) 76543210 r ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 w reset: 00000000 figure 6-11. port b data register (ptbd) table 6-10. ptbd register field descriptions field description 7:0 ptbd[7:0] port b data register bits ?for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port b pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 76543210 r ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 w reset: 00000000 figure 6-12. port b data direction register (ptbdd) table 6-11. ptbdd register field descriptions field description 7:0 ptbdd[7:0] data direction for port b bits these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 86 freescale semiconductor 6.6.2.3 port b pull enable register (ptbpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.6.2.4 port b slew rate enable register (ptbse) 76543210 r ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 w reset: 00000000 figure 6-13. internal pull enable for port b register (ptbpe) table 6-12. ptbpe register field descriptions field description 7:0 ptbpe[7:0] internal pull enable for port b bits each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated ptb pin. for port b pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port b bit n. 1 internal pull-up/pull-down device enabled for port b bit n. 76543210 r ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 w reset: 00000000 figure 6-14. slew rate enable for port b register (ptbse) table 6-13. ptbse register field descriptions field description 7:0 ptbse[7:0] output slew rate enable for port b bits each of these control bits determines if the output slew rate control is enabled for the associated ptb pin. for port b pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port b bit n. 1 output slew rate control enabled for port b bit n.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 87 6.6.2.5 port b drive strength selection register (ptbds) 6.6.2.6 port b interrupt status and control register (ptbsc) 76543210 r ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 w reset: 00000000 figure 6-15. drive strength selection for port b register (ptbds) table 6-14. ptbds register field descriptions field description 7:0 ptbds[7:0] output drive strength selection for port b bits ?each of these control bits selects between low and high output drive for the associated ptb pin. for port b pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port b bit n. 1 high output drive strength selected for port b bit n. 76543210 r0000 ptbif 0 ptbie ptbmod w ptback reset: 00000000 figure 6-16. port b interrupt status and control register (ptbsc) table 6-15. ptbsc register field descriptions field description 3 ptbif port b interrupt flag ?ptbif indicates when a port b interrupt is detected. writes have no effect on ptbif. 0 no port b interrupt detected. 1 port b interrupt detected. 2 ptback port b interrupt acknowledge ?writing a 1 to ptback is part of the ?g clearing mechanism. ptback always reads as 0. 1 ptbie port b interrupt enable ?ptbie determines whether a port b interrupt is requested. 0 port b interrupt request not enabled. 1 port b interrupt request enabled. 0 ptbmod port b detection mode ?ptbmod (along with the ptbes bits) controls the detection mode of the port b interrupt pins. 0 port b pins detect edges only. 1 port b pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 88 freescale semiconductor 6.6.2.7 port b interrupt pin select register (ptbps) 6.6.2.8 port b interrupt edge select register (ptbes) 76543210 r0000 ptbps3 ptbps2 ptbps1 ptbps0 w reset: 00000000 figure 6-17. port b interrupt pin select register (ptbps) table 6-16. ptbps register field descriptions field description 3:0 ptbps[3:0] port b interrupt pin selects ?each of the ptbpsn bits enable the corresponding port b interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r0000 ptbes3 ptbes2 ptbes1 ptbes0 w reset: 00000000 figure 6-18. port b edge select register (ptbes) table 6-17. ptbes register field descriptions field description 3:0 ptbes[3:0] port b edge selects ?each of the ptbesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 89 6.6.3 port c registers port c is controlled by the registers listed below. 6.6.3.1 port c data register (ptcd) 6.6.3.2 port c data direction register (ptcdd) 76543210 r0000 ptcd3 ptcd2 ptcd1 ptcd0 w reset: 00000000 figure 6-19. port c data register (ptcd) table 6-18. ptcd register field descriptions field description 3:0 ptcd[3:0] port c data register bits ?for port c pins that are inputs, reads return the logic level on the pin. for port c pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port c pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r0000 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset: 00000000 figure 6-20. port c data direction register (ptcdd) table 6-19. ptcdd register field descriptions field description 3:0 ptcdd[3:0] data direction for port c bits these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 90 freescale semiconductor 6.6.3.3 port c pull enable register (ptcpe) 6.6.3.4 port c slew rate enable register (ptcse) 76543210 r0000 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset: 00000000 figure 6-21. internal pull enable for port c register (ptcpe) table 6-20. ptcpe register field descriptions field description 3:0 ptcpe[3:0] internal pull enable for port c bits ?each of these control bits determines if the internal pull-up device is enabled for the associated ptc pin. for port c pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up device disabled for port c bit n. 1 internal pull-up device enabled for port c bit n. 76543210 r0000 ptcse3 ptcse2 ptcse1 ptcse0 w reset: 00000000 figure 6-22. slew rate enable for port c register (ptcse) table 6-21. ptcse register field descriptions field description 3:0 ptcse[3:0] output slew rate enable for port c bits each of these control bits determines if the output slew rate control is enabled for the associated ptc pin. for port c pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port c bit n. 1 output slew rate control enabled for port c bit n.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 91 6.6.3.5 port c drive strength selection register (ptcds) 6.6.3.6 ganged output drive control register (gngc) 76543210 r0000 ptcds3 ptcds2 ptcds1 ptcds0 w reset: 00000000 figure 6-23. drive strength selection for port c register (ptcds) table 6-22. ptcds register field descriptions field description 3:0 ptcds[3:0] output drive strength selection for port c bits ?each of these control bits selects between low and high output drive for the associated ptc pin. for port c pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port c bit n. 1 high output drive strength selected for port c bit n. 76543210 r gngps7 gngps6 gngps5 gngps4 gngps3 gngps2 gngps1 gngen w reset: 00000000 figure 6-24. ganged output drive control register (gngc) table 6-23. gngc register field descriptions field description 7:1 gngp[7:1] ganged output pin select bits ?these write-once control bits selects whether the associated pin (see table 6-1 for pins available) is enabled for ganged output. when gngen = 1, all enabled ganged output pins will be controlled by the data, drive strength and slew rate settings for ptco. 0 associated pin is not part of the ganged output drive. 1 assoicated pin is part of the ganged output drive. requires gngen = 1. 0 gngen ganged output drive enable bit this write-once control bit selects whether the ganged output drive feature is enabled. 0 ganged output drive disabled. 1 ganged output drive enabled. ptc0 forced to output regardless of the value of ptcdd0 in ptcdd.
chapter 6 parallel input/output control mc9s08sh8 mcu series data sheet, rev. 1 92 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 93 chapter 7 central processor unit (s08cpuv2) 7.1 introduction this section provides summary information about the registers, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code-compatible with the m68hc08 cpu. several instructions and enhanced addressing modes were added to improve c compiler ef?iency and to support a new background debug system which replaces the monitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: object code fully upward-compatible with m68hc05 and m68hc08 families all registers and memory are mapped to a single 64-kbyte address space 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) 16-bit index register (h:x) with powerful indexed addressing modes 8-bit accumulator (a) many instructions treat x as a second general-purpose 8-bit register seven addressing modes: inherent ?operands in internal registers relative ?8-bit signed offset to branch destination immediate ?operand in next object code byte(s) direct ?operand in memory at 0x0000?x00ff extended ?operand anywhere in 64-kbyte address space indexed relative to h:x ?five submodes including auto increment indexed relative to sp ?improves c ef?iency dramatically memory-to-memory data move instructions with four address mode combinations over?w, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ef?ient bit manipulation instructions fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions stop and wait instructions to invoke low-power operating modes
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 94 freescale semiconductor 7.2 programmers model and cpu registers figure 7-1 shows the ve cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit register. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu results are often stored into the a accumulator after arithmetic and logical operations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of a can be stored to memory using various addressing modes to specify the address where data from a will be stored. reset has no effect on the contents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit registers (h and x), which often work together as a 16-bit address pointer where h holds the upper byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8-bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or transferred to a where arithmetic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is forced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 95 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available location on the automatic last-in-?st-out (lifo) stack. the stack may be located anywhere in the 64-kbyte address space that has ram and can be any size up to the amount of available ram. the stack is used to automatically save the return address for subroutine calls, the return address and cpu registers during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ram (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was included for compatibility with the m68hc05 family and is seldom used in new hcs08 programs because it only affects the low-order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. this is called a change-of-?w. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the ?st instruction that will be executed after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contains the interrupt mask (i) and ve ?gs that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code bits in general terms. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1.
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 96 freescale semiconductor figure 7-2. condition code register table 7-1. ccr register field descriptions field description 7 v twos complement over?w flag the cpu sets the over?w ?g when a twos complement over?w occurs. the signed branch instructions bgt, bge, ble, and blt use the over?w ?g. 0 no over?w 1 over?w 4 h half-carry flag the cpu sets the half-carry ?g when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry ?g is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ?when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the ?st instruction of the interrupt service routine is executed. interrupts are not recognized at the instruction boundary after any instruction that clears i (cli or tap). this ensures that the next instruction after a cli or tap will always be executed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ?the cpu sets the negative ?g when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most signi?ant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ?the cpu sets the zero ?g when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1 zero result 0 c carry/borrow flag the cpu sets the carry/borrow ?g when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow ?g. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow 70 ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 97 7.3 addressing modes addressing modes de?e the way the cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/output (i/o) ports share a single 64-kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access variables in ram can also be used to access i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and dbnz use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. for brclr, brset, cbeq, and dbnz, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination location for branch instructions. a signed 8-bit offset value is located in the memory location immediately following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. in the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?x00ff). during execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory ef?ient than specifying a complete 16-bit address for the operand.
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 98 freescale semiconductor 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte ?st). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including ve that use the 16-bit h:x index register pair and two that use the stack pointer as the base reference. 7.3.6.1 indexed, no offset (ix) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 99 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special operations that are similar to instructions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop and wait directly affect other mcu circuitry. this section provides additional information about these operations. 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determines the source, refer to the resets, interrupts, and system con?uration chapter. the reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0xfffe and 0xffff and to ?l the instruction queue in preparation for execution of the ?st program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program information starting at the address indicated by the interrupt vector to ?l the instruction queue in preparation for execution of the ?st instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routine. although it is possible to clear the i bit with an instruction in the
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 100 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are dif?ult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the high-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt sequence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a hardware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumption while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event occurs, the cpu clocks will resume and the interrupt or reset event will be processed normally. if a serial background command is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. in such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be con?ured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodic signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial background command is issued to the mcu through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode depends on the particular hcs08 and whether the oscillator was stopped in stop mode. refer to the modes of operation chapter for more details.
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 101 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compared to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to stop processing user instructions and enter the active background mode. the only way to resume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program reaches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program.
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 102 freescale semiconductor 7.5 hcs08 instruction set summary table 7-2 provides a summary of the hcs08 instruction set in all possible addressing modes. the table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. table 7-2. instruction set summary (sheet 1 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c adc # opr8i adc opr8a adc opr16a adc oprx16,x adc oprx8,x adc ,x adc oprx16,sp adc oprx8,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9e d9 9e e9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11? ? ? ? add # opr8i add opr8a add opr16a add oprx16,x add oprx8,x add ,x add oprx16,sp add oprx8,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9e db 9e eb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11? ? ? ? ais #opr8i add immediate value (signed) to stack pointer sp (sp) + (m) imm a7 ii 2 pp ?1 aix #opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) imm af ii 2 pp ?1 and # opr8i and opr8a and opr16a and oprx16,x and oprx8,x and ,x and oprx16,sp and oprx8,sp logical and a (a) & (m) imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9e d4 9e e4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ?? asl opr8a asla aslx asl oprx8,x asl ,x asl oprx8,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ? ? ? asr opr8a asra asrx asr oprx8,x asr ,x asr oprx8,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ? ? ? c b0 b7 0 b0 b7 c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 103 bcc rel branch if carry bit clear (if c = 0) rel 24 rr 3 ppp ?1 bclr n, opr8a clear bit n in memory (mn 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?1 bcs rel branch if carry bit set (if c = 1) (same as blo) rel 25 rr 3 ppp ?1 beq rel branch if equal (if z = 1) rel 27 rr 3 ppp ?1 bge rel branch if greater than or equal to (if n v = 0) (signed) rel 90 rr 3 ppp ?1 bgnd enter active background if enbdm=1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ fp...ppp ?1 bgt rel branch if greater than (if z | (n v) = 0) (signed) rel 92 rr 3 ppp ?1 bhcc rel branch if half carry bit clear (if h = 0) rel 28 rr 3 ppp ?1 bhcs rel branch if half carry bit set (if h = 1) rel 29 rr 3 ppp ?1 bhi rel branch if higher (if c | z = 0) rel 22 rr 3 ppp ?1 bhs rel branch if higher or same (if c = 0) (same as bcc) rel 24 rr 3 ppp ?1 bih rel branch if irq pin high (if irq pin = 1) rel 2f rr 3 ppp ?1 bil rel branch if irq pin low (if irq pin = 0) rel 2e rr 3 ppp ?1 bit # opr8i bit opr8a bit opr16a bit oprx16,x bit oprx8,x bit ,x bit oprx16,sp bit oprx8,sp bit test (a) & (m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9e d5 9e e5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ble rel branch if less than or equal to (if z | (n v) = 1) (signed) rel 93 rr 3 ppp ?1 blo rel branch if lower (if c = 1) (same as bcs) rel 25 rr 3 ppp ?1 bls rel branch if lower or same (if c | z = 1) rel 23 rr 3 ppp ?1 blt rel branch if less than (if n v = 1) (signed) rel 91 rr 3 ppp ?1 bmc rel branch if interrupt mask clear (if i = 0) rel 2c rr 3 ppp ?1 bmi rel branch if minus (if n = 1) rel 2b rr 3 ppp ?1 bms rel branch if interrupt mask set (if i = 1) rel 2d rr 3 ppp ?1 bne rel branch if not equal (if z = 0) rel 26 rr 3 ppp ?1 table 7-2. instruction set summary (sheet 2 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 104 freescale semiconductor bpl rel branch if plus (if n = 0) rel 2a rr 3 ppp ?1 bra rel branch always (if i = 1) rel 20 rr 3 ppp ?1 brclr n , opr8a , rel branch if bit n in memory clear (if (mn) = 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?1 ? brn rel branch never (if i = 0) rel 21 rr 3 ppp ?1 brset n , opr8a , rel branch if bit n in memory set (if (mn) = 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?1 ? bset n, opr8a set bit n in memory (mn 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?1 bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc (pc) + rel rel ad rr 5 ssppp ?1 cbeq opr8a , rel cbeqa # opr8i , rel cbeqx # opr8i , rel cbeq oprx8 ,x+,rel cbeq ,x+, rel cbeq oprx8,sp,rel compare and... branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp ?1 clc clear carry bit (c 0) inh 98 1 p ?1? cli clear interrupt mask bit (i 0) inh 9a 1 p ?10 clr opr8a clra clrx clrh clr oprx8,x clr ,x clr oprx8,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e 6f dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 011?1 table 7-2. instruction set summary (sheet 3 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 105 cmp #opr8i cmp opr8a cmp opr16a cmp oprx16,x cmp oprx8,x cmp ,x cmp oprx16,sp cmp oprx8,sp compare accumulator with memory a ?m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9e d1 9e e1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? com opr8a coma comx com oprx8,x com ,x com oprx8,sp complement m ( m)= $ff ?(m) (one? complement) a ( a) = $ff ?(a) x ( x) = $ff ?(x) m ( m) = $ff ?(m) m ( m) = $ff ?(m) m ( m) = $ff ?(m) dir inh inh ix1 ix sp1 33 43 53 63 73 9e 63 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 011 ??1 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8,sp compare index register (h:x) with memory (h:x) ?(m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9e f3 hh ll jj kk dd ff 6 3 5 6 prrfpp ppp rrfpp prrfpp ? 11 ? ? ? cpx # opr8i cpx opr8a cpx opr16a cpx oprx16,x cpx oprx8,x cpx ,x cpx oprx16,sp cpx oprx8 ,sp compare x (index register low) with memory x ?m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9e d3 9e e3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? daa decimal adjust accumulator after add or adc of bcd values inh 72 1 p u11 ? ? ? dbnz opr8a, rel dbnza rel dbnzx rel dbnz oprx8,x, rel dbnz ,x, rel dbnz oprx8,sp,rel decrement a, x, or m and branch if not zero (if (result) 0) dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e 6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 rfwpppp fppp fppp rfwpppp rfwppp prfwpppp ?1 dec opr8a deca decx dec oprx8,x dec ,x dec oprx8,sp decrement m (m) ?$01 a (a) ?$01 x (x) ?$01 m (m) ?$01 m (m) ?$01 m (m) ?$01 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e 6a dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ?? div divide a (h:a)(x); h remainder inh 52 6 fffffp ?1 ?? eor #opr8i eor opr8a eor opr16a eor oprx16,x eor oprx8,x eor ,x eor oprx16,sp eor oprx8,sp exclusive or memory with accumulator a (a m) imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9e d8 9e e8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ?? table 7-2. instruction set summary (sheet 4 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 106 freescale semiconductor inc opr8a inca incx inc oprx8,x inc ,x inc oprx8,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e 6c dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 jmp opr8a jmp opr16a jmp oprx16,x jmp oprx8,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 ppp pppp pppp ppp ppp ?1 jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 ssppp pssppp pssppp ssppp ssppp ?1 lda # opr8i lda opr8a lda opr16a lda oprx16,x lda oprx8,x lda ,x lda oprx16,sp lda oprx8,sp load accumulator from memory a (m) imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9e d6 9e e6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ldhx #opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16,x ldhx oprx8,x ldhx oprx8,sp load index register (h:x) h:x ( m:m + $0001 ) imm dir ext ix ix2 ix1 sp1 45 55 32 9e ae 9e be 9e ce 9e fe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ppp rrpp prrpp prrfp pprrpp prrpp prrpp 011 ldx # opr8i ldx opr8a ldx opr16a ldx oprx16,x ldx oprx8,x ldx ,x ldx oprx16,sp ldx oprx8,sp load x (index register low) from memory x (m) imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9e de 9e ee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 lsl opr8a lsla lslx lsl oprx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 lsr opr8a lsra lsrx lsr oprx8,x lsr ,x lsr oprx8,sp logical shift right dir inh inh ix1 ix sp1 34 44 54 64 74 9e 64 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 110 table 7-2. instruction set summary (sheet 5 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c c b0 b7 0 b0 b7 c 0
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 107 mov opr8a, opr8a mov opr8a ,x+ mov #opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source in ix+/dir and dir/ix+ modes, h:x (h:x) + $0001 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 rpwpp rfwpp pwpp rfwpp 011 mul unsigned multiply x:a (x) (a) inh 42 5 ffffp 110? neg opr8a nega negx neg oprx8,x neg ,x neg oprx8,sp negate m ?(m) = $00 ?(m) (two? complement) a ?(a) = $00 ?(a) x ?(x) = $00 ?(x) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e 60 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 nop no operation ?uses 1 bus cycle inh 9d 1 p ?1 nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 p ?1 ora #opr8i ora opr8a ora opr16a ora oprx16,x ora oprx8,x ora ,x ora oprx16,sp ora oprx8,sp inclusive or accumulator and memory a (a) | (m) imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9e da 9e ea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 psha push accumulator onto stack push (a); sp (sp) ?$0001 inh 87 2 sp ?1 pshh push h (index register high) onto stack push (h); sp (sp) ?$0001 inh 8b 2 sp ?1 pshx push x (index register low) onto stack push (x); sp (sp) ?$0001 inh 89 2 sp ?1 pula pull accumulator from stack sp (sp + $0001); pull ( a) inh 86 3 ufp ?1 pulh pull h (index register high) from stack sp (sp + $0001); pull ( h) inh 8a 3 ufp ?1 pulx pull x (index register low) from stack sp (sp + $0001); pull ( x) inh 88 3 ufp ?1 rol opr8a rola rolx rol oprx8,x rol ,x rol oprx8,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e 69 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ror opr8a rora rorx ror oprx8,x ror ,x ror oprx8,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e 66 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 table 7-2. instruction set summary (sheet 6 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c c b0 b7 b0 b7 c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 108 freescale semiconductor rsp reset stack pointer (low byte) spl $ff (high byte not affected) inh 9c 1 p ?1 rti return from interrupt sp (sp) + $0001; pull (ccr) sp (sp) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 uuuuufppp ? 11 ? ? ? ? ? rts return from subroutine sp sp + $0001 ; pull ( pch) sp sp + $0001; pull (pcl) inh 81 5 ufppp ?1 sbc # opr8i sbc opr8a sbc opr16a sbc oprx16,x sbc oprx8,x sbc ,x sbc oprx16,sp sbc oprx8 ,sp subtract with carry a (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9e d2 9e e2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? sec set carry bit (c 1) inh 99 1 p ?1? sei set interrupt mask bit (i 1) inh 9b 1 p ?1 1 sta opr8a sta opr16a sta oprx16,x sta oprx8,x sta ,x sta oprx16,sp sta oprx8,sp store accumulator in memory m (a) dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9e d7 9e e7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011 ?? sthx opr8a sthx opr16a sthx oprx8,sp store h:x (index reg.) (m:m + $0001) (h:x) dir ext sp1 35 96 9e ff dd hh ll ff 4 5 5 wwpp pwwpp pwwpp 011 ?? stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing inh 8e 2 fp... ?10 stx opr8a stx opr16a stx oprx16,x stx oprx8,x stx ,x stx oprx16,sp stx oprx8,sp store x (low 8 bits of index register) in memory m (x) dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9e df 9e ef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011 ?? table 7-2. instruction set summary (sheet 7 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 109 sub # opr8i sub opr8a sub opr16a sub oprx16,x sub oprx8,x sub ,x sub oprx16,sp sub oprx8 ,sp subtract a (a) ?(m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9e d0 9e e0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 swi software interrupt pc (pc) + $0001 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 push (x); sp (sp) ?$0001 push (a); sp (sp) ?$0001 push (ccr); sp (sp) ?$0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte inh 83 11 sssssvvfppp ?11 tap transfer accumulator to ccr ccr (a) inh 84 1 p 11 tax transfer accumulator to x (index register low) x (a) inh 97 1 p ?1 tpa transfer ccr to accumulator a (ccr) inh 85 1 p ?1 tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ?$00 (a) ?$00 (x) ?$00 (m) ?$00 (m) ?$00 (m) ?$00 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e 6d dd ff ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 011 tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 fp ?1 txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 p ?1 table 7-2. instruction set summary (sheet 8 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 110 freescale semiconductor txs transfer index reg. to sp sp (h:x) ?$0001 inh 94 2 fp ?1 wait enable interrupts; wait for interrupt i bit 0; halt cpu inh 8f 2+ fp... ?10 source form: everything in the source forms columns, except expressions in italic characters , is literal information which must appear in the assembly source ?e exactly as shown. the initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal characters. n any label or expression that evaluates to a single integer in the range 0-7. opr8i any label or expression that evaluates to an 8-bit immediate value. opr16i any label or expression that evaluates to a 16-bit immediate value. opr8a any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a any label or expression that evaluates to a 16-bit address. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel any label or expression that refers to an address that is within ?28 to +127 locations from the start of the next instruction. operation symbols: a accumulator ccr condition code register h index register high byte m memory location n any bit opr operand (one or two bytes) pc program counter pch program counter high byte pcl program counter low byte rel relative program counter offset byte sp stack pointer spl stack pointer low byte x index register low byte & logical and | logical or logical exclusive or ( ) contents of + add subtract, negation (twos complement) multiply divide # immediate value loaded with : concatenated with addressing modes: dir direct addressing mode ext extended addressing mode imm immediate addressing mode inh inherent addressing mode ix indexed, no offset addressing mode ix1 indexed, 8-bit offset addressing mode ix2 indexed, 16-bit offset addressing mode ix+ indexed, no offset, post increment addressing mode ix1+ indexed, 8-bit offset, post increment addressing mode rel relative addressing mode sp1 stack pointer, 8-bit offset addressing mode sp2 stack pointer 16-bit offset addressing mode cycle-by-cycle codes: f free cycle. this indicates a cycle where the cpu does not require use of the system buses. an f cycle is always one cycle of the system bus clock and is always a read cycle. p program fetch; read from next consecutive location in program memory r read 8-bit operand s push (write) one byte onto stack u pop (read) one byte from stack v read vector from $ffxx (high byte ?st) w write 8-bit operand ccr bits: v over?w bit h half-carry bit i interrupt mask n negative bit z zero bit c carry/borrow bit ccr effects: set or cleared not affected u unde?ed table 7-2. instruction set summary (sheet 9 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 11 h i n z c
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 111 table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modify-write control register/memory 00 5 brset0 3 dir 10 5 bset0 2 dir 20 3 bra 2 rel 30 5 neg 2 dir 40 1 nega 1 inh 50 1 negx 1 inh 60 5 neg 2 ix1 70 4 neg 1ix 80 9 rti 1 inh 90 3 bge 2 rel a0 2 sub 2 imm b0 3 sub 2 dir c0 4 sub 3 ext d0 4 sub 3 ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3 dir 11 5 bclr0 2 dir 21 3 brn 2 rel 31 5 cbeq 3 dir 41 4 cbeqa 3 imm 51 4 cbeqx 3imm 61 5 cbeq 3 ix1+ 71 5 cbeq 2 ix+ 81 6 rts 1 inh 91 3 blt 2 rel a1 2 cmp 2 imm b1 3 cmp 2 dir c1 4 cmp 3 ext d1 4 cmp 3 ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3 dir 12 5 bset1 2 dir 22 3 bhi 2 rel 32 5 ldhx 3 ext 42 5 mul 1 inh 52 6 div 1 inh 62 1 nsa 1 inh 72 1 daa 1 inh 82 5+ bgnd 1 inh 92 3 bgt 2 rel a2 2 sbc 2 imm b2 3 sbc 2 dir c2 4 sbc 3 ext d2 4 sbc 3 ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3 dir 13 5 bclr1 2 dir 23 3 bls 2 rel 33 5 com 2 dir 43 1 coma 1 inh 53 1 comx 1 inh 63 5 com 2 ix1 73 4 com 1ix 83 11 swi 1 inh 93 3 ble 2 rel a3 2 cpx 2 imm b3 3 cpx 2 dir c3 4 cpx 3 ext d3 4 cpx 3 ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3 dir 14 5 bset2 2 dir 24 3 bcc 2 rel 34 5 lsr 2 dir 44 1 lsra 1 inh 54 1 lsrx 1 inh 64 5 lsr 2 ix1 74 4 lsr 1ix 84 1 ta p 1 inh 94 2 txs 1 inh a4 2 and 2 imm b4 3 and 2 dir c4 4 and 3 ext d4 4 and 3 ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3 dir 15 5 bclr2 2 dir 25 3 bcs 2 rel 35 4 sthx 2 dir 45 3 ldhx 3 imm 55 4 ldhx 2 dir 65 3 cphx 3imm 75 5 cphx 2 dir 85 1 tpa 1 inh 95 2 tsx 1 inh a5 2 bit 2 imm b5 3 bit 2 dir c5 4 bit 3 ext d5 4 bit 3 ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3 dir 16 5 bset3 2 dir 26 3 bne 2 rel 36 5 ror 2 dir 46 1 rora 1 inh 56 1 rorx 1 inh 66 5 ror 2 ix1 76 4 ror 1ix 86 3 pula 1 inh 96 5 sthx 3 ext a6 2 lda 2 imm b6 3 lda 2 dir c6 4 lda 3 ext d6 4 lda 3 ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3 dir 17 5 bclr3 2 dir 27 3 beq 2 rel 37 5 asr 2 dir 47 1 asra 1 inh 57 1 asrx 1 inh 67 5 asr 2 ix1 77 4 asr 1ix 87 2 psha 1 inh 97 1 ta x 1 inh a7 2 ais 2 imm b7 3 sta 2 dir c7 4 sta 3 ext d7 4 sta 3 ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3 dir 18 5 bset4 2 dir 28 3 bhcc 2 rel 38 5 lsl 2 dir 48 1 lsla 1 inh 58 1 lslx 1 inh 68 5 lsl 2 ix1 78 4 lsl 1ix 88 3 pulx 1 inh 98 1 clc 1 inh a8 2 eor 2 imm b8 3 eor 2 dir c8 4 eor 3 ext d8 4 eor 3 ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3 dir 19 5 bclr4 2 dir 29 3 bhcs 2 rel 39 5 rol 2 dir 49 1 rola 1 inh 59 1 rolx 1 inh 69 5 rol 2 ix1 79 4 rol 1ix 89 2 pshx 1 inh 99 1 sec 1 inh a9 2 adc 2 imm b9 3 adc 2 dir c9 4 adc 3 ext d9 4 adc 3 ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3 dir 1a 5 bset5 2 dir 2a 3 bpl 2 rel 3a 5 dec 2 dir 4a 1 deca 1 inh 5a 1 decx 1 inh 6a 5 dec 2 ix1 7a 4 dec 1ix 8a 3 pulh 1 inh 9a 1 cli 1 inh aa 2 ora 2 imm ba 3 ora 2 dir ca 4 ora 3 ext da 4 ora 3 ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3 dir 1b 5 bclr5 2 dir 2b 3 bmi 2 rel 3b 7 dbnz 3 dir 4b 4 dbnza 2 inh 5b 4 dbnzx 2 inh 6b 7 dbnz 3 ix1 7b 6 dbnz 2ix 8b 2 pshh 1 inh 9b 1 sei 1 inh ab 2 add 2 imm bb 3 add 2 dir cb 4 add 3 ext db 4 add 3 ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3 dir 1c 5 bset6 2 dir 2c 3 bmc 2 rel 3c 5 inc 2 dir 4c 1 inca 1 inh 5c 1 incx 1 inh 6c 5 inc 2 ix1 7c 4 inc 1ix 8c 1 clrh 1 inh 9c 1 rsp 1 inh bc 3 jmp 2 dir cc 4 jmp 3 ext dc 4 jmp 3 ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3 dir 1d 5 bclr6 2 dir 2d 3 bms 2 rel 3d 4 tst 2 dir 4d 1 tsta 1 inh 5d 1 tstx 1 inh 6d 4 tst 2 ix1 7d 3 tst 1ix 9d 1 nop 1 inh ad 5 bsr 2 rel bd 5 jsr 2 dir cd 6 jsr 3 ext dd 6 jsr 3 ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3 dir 1e 5 bset7 2 dir 2e 3 bil 2 rel 3e 6 cphx 3 ext 4e 5 mov 3dd 5e 5 mov 2 dix+ 6e 4 mov 3imd 7e 5 mov 2 ix+d 8e 2+ stop 1 inh 9e page 2 ae 2 ldx 2 imm be 3 ldx 2 dir ce 4 ldx 3 ext de 4 ldx 3 ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3 dir 1f 5 bclr7 2 dir 2f 3 bih 2 rel 3f 5 clr 2 dir 4f 1 clra 1 inh 5f 1 clrx 1 inh 6f 5 clr 2 ix1 7f 4 clr 1ix 8f 2+ wait 1 inh 9f 1 txa 1 inh af 2 aix 2 imm bf 3 stx 2 dir cf 4 stx 3 ext df 4 stx 3 ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 7 central processor unit (s08cpuv2) mc9s08sh8 mcu series data sheet, rev. 1 112 freescale semiconductor bit-manipulation branch read-modify-write control register/memory 9e60 6 neg 3 sp1 9ed0 5 sub 4 sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4 sp1 9ed1 5 cmp 4 sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4 sp2 9ee2 4 sbc 3sp1 9e63 6 com 3 sp1 9ed3 5 cpx 4 sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3 sp1 9e64 6 lsr 3 sp1 9ed4 5 and 4 sp2 9ee4 4 and 3sp1 9ed5 5 bit 4 sp2 9ee5 4 bit 3sp1 9e66 6 ror 3 sp1 9ed6 5 lda 4 sp2 9ee6 4 lda 3sp1 9e67 6 asr 3 sp1 9ed7 5 sta 4 sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3 sp1 9ed8 5 eor 4 sp2 9ee8 4 eor 3sp1 9e69 6 rol 3 sp1 9ed9 5 adc 4 sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3 sp1 9eda 5 ora 4 sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4 sp1 9edb 5 add 4 sp2 9eeb 4 add 3sp1 9e6c 6 inc 3 sp1 9e6d 5 tst 3 sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4 ix2 9ece 5 ldhx 3 ix1 9ede 5 ldx 4 sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3 sp1 9e6f 6 clr 3 sp1 9edf 5 stx 4 sp2 9eef 4 stx 3sp1 9eff 5 sthx 3 sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3 sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2)
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 113 chapter 8 analog comparator 5-v (s08acmpv2) 8.1 introduction the analog comparator module (acmp) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. the comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). figure 8-1 shows the mc9s08sh8 block diagram with the acmp highlighted. 8.1.1 acmp con?uration information when using the bandgap reference voltage for input to acmp+, the user must enable the bandgap buffer by setting bgbe =1 in spmsc1 see section 5.7.7, ?ystem power management status and control 1 register (spmsc1) ? for value of bandgap voltage reference see section a.6, ?c characteristics ? 8.1.2 acmp in stop3 mode s08acmpv2 continues to operate in stop3 mode if enabled. if acope is enabled, comparator output will operate as in the normal operating mode and will control acmpo pin. the mcu is brought out of stop when a compare event occurs and acie is enabled; acf ?g sets accordingly. 8.1.3 acmp/tpm con?uration information the acmp module can be con?ured to connect the output of the analog comparator to tpm1 input capture channel 0 by setting acic in sopt2. with acic set, the tpm1ch0 pin is not available externally regardless of the con?uration of the tpm1 module for channel 0.
chapter 8 analog comparator 5-v (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 114 freescale semiconductor figure 8-1. mc9s08sh8 block diagram highlighting the acmp module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 115 8.1.4 features the acmp has the following features: full rail to rail supply operation. selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. option to compare to ?ed internal bandgap reference voltage. option to allow comparator output to be visible on a pin, acmpo. can operate in stop3 mode 8.1.5 modes of operation this section de?es the acmp operation in wait, stop and background debug modes. 8.1.5.1 acmp in wait mode the acmp continues to run in wait mode if enabled before executing the wait instruction. therefore, the acmp can be used to bring the mcu out of wait mode if the acmp interrupt, acie is enabled. for lowest possible current consumption, the acmp should be disabled by software if not required as an interrupt source during wait mode. 8.1.5.2 acmp in stop modes 8.1.5.2.1 stop3 mode operation the acmp continues to operate in stop3 mode if enabled and compare operation remains active. if acope is enabled, comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. the mcu is brought out of stop when a compare event occurs and acie is enabled; acf ?g sets accordingly. if stop is exited with a reset, the acmp will be put into its reset state. 8.1.5.2.2 stop2 and stop1 mode operation during either stop2 and stop1 mode, the acmp module will be fully powered down. upon wake-up from stop2 or stop1 mode, the acmp module will be in the reset state. 8.1.5.3 acmp in active background mode when the microcontroller is in active background mode, the acmp will continue to operate normally. 8.1.6 block diagram the block diagram for the analog comparator module is shown figure 8-2 .
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 116 freescale semiconductor figure 8-2. analog comparator 5v (acmp5) block diagram + - interrupt control internal reference acbgs internal bus status & control register acmod set acf acme acf acie acope comparator acmp interrupt request acmp+ acmp- acmpo
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 117 8.2 external signal description the acmp has two analog input pins, acmp+ and acmp- and one digital output pin acmpo. each of these pins can accept an input voltage that varies across the full operating voltage range of the mcu. as shown in figure 8-2 , the acmp- pin is connected to the inverting input of the comparator, and the acmp+ pin is connected to the comparator non-inverting input if acbgs is a 0. as shown in figure 8-2 , the acmpo pin can be enabled to drive an external pin. the signal properties of acmp are shown in table 8-1 . 8.3 memory map 8.3.1 register descriptions the acmp includes one register: an 8-bit status and control register refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all acmp registers.this section refers to registers and control bits only by their names . some mcus may have more than one acmp, so register names include placeholder characters to identify which acmp is being referenced. table 8-1. signal properties signal function i/o acmp- inverting analog input to the acmp. (minus input) i acmp+ non-inverting analog input to the acmp. (positive input) i acmpo digital output of the acmp. o
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 118 freescale semiconductor 8.3.1.1 acmp status and control register (acmpsc) acmpsc contains the status ?g and control bits which are used to enable and con?ure the acmp. 76543210 r acme acbgs acf acie aco acope acmod w reset: 0 0 0 0 0 0 0 0 = unimplemented figure 8-3. acmp status and control register table 8-2. acmp status and control register field descriptions field description 7 acme analog comparator module enable ?acme enables the acmp module. 0 acmp not enabled 1 acmp is enabled 6 acbgs analog comparator bandgap select ?acbgs is used to select between the bandgap reference voltage or the acmp+ pin as the input to the non-inverting input of the analog comparatorr. 0 external pin acmp+ selected as non-inverting input to comparator 1 internal reference select as non-inverting input to comparator note: refer to this chapter introduction to verify if any other con? bits are necessary to enable the bandgap reference in the chip level. 5 acf analog comparator flag acf is set when a compare event occurs. compare events are de?ed by acmod. acf is cleared by writing a one to acf. 0 compare event has not occured 1 compare event has occured 4 acie analog comparator interrupt enable ?acie enables the interrupt from the acmp. when acie is set, an interupt will be asserted when acf is set. 0 interrupt disabled 1 interrupt enabled 3 aco analog comparator output reading aco will return the current value of the analog comparator output. aco is reset to a 0 and will read as a 0 when the acmp is disabled (acme = 0). 2 acope analog comparator output pin enable acope is used to enable the comparator output to be placed onto the external pin, acmpo. 0 analog comparator output not available on acmpo 1 analog comparator output is driven out on acmpo 1:0 acmod analog comparator mode ?acmod selects the type of compare event which sets acf. 00 encoding 0 ?comparator output falling edge 01 encoding 1 ?comparator output rising edge 10 encoding 2 ?comparator output falling edge 11 encoding 3 ?comparator output rising or falling edge
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 119 8.4 functional description the analog comparator can be used to compare two analog input voltages applied to acmp+ and acmp-; or it can be used to compare an analog input voltage applied to acmp- with an internal bandgap reference voltage. acbgs is used to select between the bandgap reference voltage or the acmp+ pin as the input to the non-inverting input of the analog comparator. the comparator output is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. acmod is used to select the condition which will cause acf to be set. acf can be set on a rising edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge (toggle). the comparator output can be read directly through aco. the comparator output can be driven onto the acmpo pin using acope.
chapter 8 analog comparator (s08acmpv2) mc9s08sh8 mcu series data sheet, rev. 1 120 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 121 chapter 9 analog-to-digital converter (s08adcv1) 9.1 introduction the 10-bit analog-to-digital converter (adc) is a successive approximation adc designed for operation within an integrated microcontroller system-on-chip. note the mc9s08sh8 family of devices do not include stop1 mode. the adc channel assignments, alternate clock function, and hardware trigger function are con?ured as described below for the mc9s08sh8 family of devices. 9.1.1 channel assignments the adc channel assignments for the mc9s08sh8 devices are shown in table 9-1 . reserved channels convert to an unknown value. table 9-1. adc channel assignment adch channel input adch channel input 00000 ad0 pta0/adp0 10000 ad16 v ss 00001 ad1 pta1/adp1 10001 ad17 v ss 00010 ad2 pta2/adp2 10010 ad18 v ss 00011 ad3 pta3/adp3 10011 ad19 v ss 00100 ad4 ptb0/adp4 10100 ad20 v ss 00101 ad5 ptb1/adp5 10101 ad21 reserved 00110 ad6 ptb2/adp6 10110 ad22 reserved 00111 ad7 ptb3/adp7 10111 ad23 reserved 01000 ad8 ptc0/adp8 11000 ad24 reserved 01001 ad9 ptc1/adp9 11001 ad25 reserved 01010 ad10 ptc2/adp10 11010 ad26 temperature sensor 1 1 for information, see section 9.1.4, ?emperature sensor ? 01011 ad11 ptc3/adp11 11011 ad27 internal bandgap 2 2 requires bgbe =1 in spmsc1 see section 5.7.8, ?ystem power management status and control 2 register (spmsc2) ? for value of bandgap voltage reference see section a.6, ?c characteristics ? 01100 ad12 v ss 11100 - reserved 01101 ad13 v ss 11101 v refh v dd 01110 ad14 v ss 11110 v refl v ss 01111 ad15 v ss 11111 module disabled none
chapter 9 analog-to-digital converter (s08adcv1) mc9s08sh8 mcu series data sheet, rev. 1 122 freescale semiconductor 9.1.2 alternate clock the adc module is capable of performing conversions using the mcu bus clock, the bus clock divided by two, the local asynchronous clock (adack) within the module, or the alternate clock, altclk. the alternate clock for the mc9s08sh8 mcu devices is the external reference clock (icserclk). the selected clock source must run at a frequency such that the adc conversion clock (adck) runs at a frequency within its speci?d range (f adck ) after being divided down from the altclk input as determined by the adiv bits. altclk is active while the mcu is in wait mode provided the conditions described above are met. this allows altclk to be used as the conversion clock source for the adc while the mcu is in wait mode. altclk cannot be used as the adc conversion clock source while the mcu is in either stop2 or stop3. 9.1.3 hardware trigger the adc hardware trigger, adhwt, is the output from the real time counter (rtc). the rtc counter can be clocked by either icserclk, icsirclk or a nominal 1 khz clock source. the period of the rtc is determined by the input clock frequency, the rtcps bits, and the rtcmod register. when the adc hardware trigger is enabled, a conversion is initiated upon an rtc counter over?w. the rtie does not have to be set for rtc to cause a hardware trigger. the rtc can be con?ured to cause a hardware trigger in mcu run, wait, and stop3. 9.1.4 temperature sensor to use the on-chip temperature sensor, the user must perform the following: con?ure adc for long sample with a maximum of 1 mhz clock convert the bandgap voltage reference channel (ad27) by converting the digital value of the bandgap voltage reference channel using the value of v bg the user can determine v dd . for value of bandgap voltage, see section a.6, ?c characteristics? convert the temperature sensor channel (ad26) by using the calculated value of v dd , convert the digital value of ad26 into a voltage, v temp equation 9-1 provides an approximate transfer function of the on-chip temperature sensor for v dd = 5.0v, temp = 25 c, using the adc1 at f adck = 1.0mhz and con?ured for long sample. temp c = 25 - ( (v temp - 0.7013) / 0.0017 ) eqn. 9-1 0.0017 is the uncalibrated voltage versus temperature slope in v/ c. uncalibrated accuracy of the temperature sensor is approximately 12c, using equation 9-1 . to improve accuracy the user should calibrate the bandgap voltage reference and temperature sensor. calibrating at 25 c will improve accuracy to 4.5c.
chapter 9 analog-to-digital converter (s08adcv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 123 calibration at 3 points, -40c, 25c, and 125 c will improve accuracy to 2.5c. once calibration has been completed, the user will need to calculate the slope for both hot and cold. in application code, the user would then calculate the temperature using equation 9-1 as detailed above and then determine if the temperature is above or below 25 c. once determined if the temperature is above or below 25 c, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. figure 9-1 shows the mc9s08sh8 with the adc module highlighted.
chapter 9 analog-to-digital converter (s08adcv1) mc9s08sh8 mcu series data sheet, rev. 1 124 freescale semiconductor figure 9-1. mc9s08sh8 block diagram highlighting the adc module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk 16-bit timer/pwm module (tpm2) tclk analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3 user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal bkgd/ms real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) irq irq (MC9S08SH4 = 256 bytes)
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 125 9.1.5 features features of the adc module include: linear successive approximation algorithm with 10 bits resolution. up to 28 analog inputs. output formatted in 10- or 8-bit right-justi?d format. single or continuous conversion (automatic return to idle after single conversion). con?urable sample time and conversion speed/power. conversion complete ?g and interrupt. input clock selectable from up to four sources. operation in wait or stop3 modes for lower noise operation. asynchronous clock source for lower noise operation. selectable asynchronous hardware conversion trigger. automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 9.1.6 block diagram figure 9-2 provides a block diagram of the adc module
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 126 freescale semiconductor figure 9-2. adc block diagram 9.2 external signal description the adc module supports up to 28 separate analog inputs. it also requires four supply/reference/ground connections. table 9-2. signal properties name function ad27?d0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ?? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adccfg adcsc1 adcsc2
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 127 9.2.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external ?tering may be necessary to ensure clean v ddad for good results. 9.2.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 9.2.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter. in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad , or may be driven by an external source that is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 9.2.4 voltage reference low (v refl ) v refl is the low reference voltage for the converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 9.2.5 analog channel inputs (adx) the adc module supports up to 28 separate analog inputs. an input is selected for conversion through the adch channel select bits. 9.3 register de?ition these memory mapped registers control and monitor operation of the adc: status and control register, adcsc1 status and control register, adcsc2 data result registers, adcrh and adcrl compare value registers, adccvh and adccvl con?uration register, adccfg pin enable registers, apctl1, apctl2, apctl3 9.3.1 status and control register 1 (adcsc1) this section describes the function of the adc status and control register (adcsc1). writing adcsc1 aborts the current conversion and initiates a new conversion (if the adch bits are equal to a value other than all 1s).
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 128 freescale semiconductor 7654 3 210 r coco aien adco adch w reset: 0 0 0 1 1 1 1 1 = unimplemented or reserved figure 9-3. status and control register (adcsc1) table 9-3. adcsc1 register field descriptions field description 7 coco conversion complete flag ?the coco ?g is a read-only bit which is set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compare function is enabled (acfe = 1) the coco ?g is set upon completion of a conversion only if the compare result is true. this bit is cleared whenever adcsc1 is written or whenever adcrl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable ?aien is used to enable conversion complete interrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable ?adco is used to enable continuous conversions. 0 one conversion following a write to the adcsc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adcsc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select the adch bits form a 5-bit ?ld which is used to select one of the input channels. the input channels are detailed in figure 9-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set to 1. this feature allows for explicit disabling of the adc and isolation of the input channel from all sources. terminating continuous conversions this way will prevent an additional, single conversion from being performed. it is not necessary to set the channel select bits to all 1s to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. figure 9-4. input channel select adch input select adch input select 00000 ad0 10000 ad16 00001 ad1 10001 ad17 00010 ad2 10010 ad18 00011 ad3 10011 ad19 00100 ad4 10100 ad20 00101 ad5 10101 ad21 00110 ad6 10110 ad22 00111 ad7 10111 ad23
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 129 9.3.2 status and control register 2 (adcsc2) the adcsc2 register is used to control the compare function, conversion trigger and conversion active of the adc module. figure 9-5. status and control register 2 (adcsc2) 01000 ad8 11000 ad24 01001 ad9 11001 ad25 01010 ad10 11010 ad26 01011 ad11 11011 ad27 01100 ad12 11100 reserved 01101 ad13 11101 v refh 01110 ad14 11110 v refl 01111 ad15 11111 module disabled 7654 3 210 radact adtrg acfe acfgt 00 r 1 1 bits 1 and 0 are reserved bits that must always be written to 0. r 1 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved table 9-4. adcsc2 register field descriptions field description 7 adact conversion active ?adact indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select adtrg is used to select the type of trigger to be used for initiating a conversion. two types of trigger are selectable: software trigger and hardware trigger. when software trigger is selected, a conversion is initiated following a write to adcsc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected figure 9-4. input channel select (continued) adch input select adch input select
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 130 freescale semiconductor 9.3.3 data result high register (adcrh) adcrh contains the upper two bits of the result of a 10-bit conversion. when con?ured for 8-bit conversions both adr8 and adr9 are equal to zero. adcrh is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until after the next conversion is completed, then the intermediate conversion result will be lost. in 8-bit mode there is no interlocking with adcrl. in the case that the mode bits are changed, any data in adcrh becomes invalid. 9.3.4 data result low register (adcrl) adcrl contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. in 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until the after next conversion is completed, then the intermediate conversion results will be lost. in 8-bit mode, there is no interlocking with adcrh. in the case that the mode bits are changed, any data in adcrl becomes invalid. 5 acfe compare function enable ?acfe is used to enable the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable acfgt is used to con?ure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare level 1 compare triggers when input is greater than or equal to compare level 7 654 3 210 r 0 0 0 0 0 0 adr9 adr8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 9-6. data result high register (adcrh) table 9-4. adcsc2 register field descriptions (continued) field description
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 131 9.3.5 compare value high register (adccvh) this register holds the upper two bits of the 10-bit compare value. these bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.in 8-bit operation, adccvh is not used during compare. 9.3.6 compare value low register (adccvl) this register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value. bits adcv7:adcv0 are compared to the lower 8 bits of the result following a conversion in either 10-bit or 8-bit mode. 9.3.7 con?uration register (adccfg) adccfg is used to select the mode of operation, clock source, clock divide, and con?ure for low power or long sample time. 7 654 3 210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 9-7. data result low register (adcrl) 7654 3 210 r0000 adcv9 adcv8 w reset: 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 9-8. compare value high register (adccvh) 7 654 3 210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset: 0 0 0 0 0 0 0 0 figure 9-9. compare value low register(adccvl)
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 132 freescale semiconductor 7654 3 210 r adlpc adiv adlsmp mode adiclk w reset: 0 0 0 0 0 0 0 0 figure 9-10. con?uration register (adccfg) table 9-5. adccfg register field descriptions field description 7 adlpc low power con?uration ?adlpc controls the speed and power con?uration of the successive approximation converter. this is used to optimize power consumption when higher sample rates are not required. 0 high speed con?uration 1 low power con?uration: {fc31}the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select ?adiv select the divide ratio used by the adc to generate the internal clock adck. table 9-6 shows the available clock con?urations. 4 adlsmp long sample time con?uration adlsmp selects between long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 short sample time 1 long sample time 3:2 mode conversion mode selection ?mode bits are used to select between 10- or 8-bit operation. see table 9-7 . 1:0 adiclk input clock select ?adiclk bits select the input clock source to generate the internal clock adck. see table 9-8 . table 9-6. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 9-7. conversion modes mode mode description 00 8-bit conversion (n=8) 01 reserved 10 10-bit conversion (n=10) 11 reserved
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 133 9.3.8 pin control 1 register (apctl1) the pin control registers are used to disable the i/o port control of mcu pins used as analog inputs. apctl1 is used to control the pins associated with channels 0? of the adc module. table 9-8. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w reset: 0 0 0 0 0 0 0 0 figure 9-11. pin control 1 register (apctl1) table 9-9. apctl1 register field descriptions field description 7 adpc7 adc pin control 7 ?adpc7 is used to control the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6 ?adpc6 is used to control the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled 5 adpc5 adc pin control 5 ?adpc5 is used to control the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4 ?adpc4 is used to control the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3 ?adpc3 is used to control the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2 ?adpc2 is used to control the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 134 freescale semiconductor 9.3.9 pin control 2 register (apctl2) apctl2 is used to control channels 8?5 of the adc module. 1 adpc1 adc pin control 1 ?adpc1 is used to control the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0 ?adpc0 is used to control the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset: 0 0 0 0 0 0 0 0 figure 9-12. pin control 2 register (apctl2) table 9-10. apctl2 register field descriptions field description 7 adpc15 adc pin control 15 ?adpc15 is used to control the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14 ?adpc14 is used to control the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13 ?adpc13 is used to control the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled 4 adpc12 adc pin control 12 ?adpc12 is used to control the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11 ?adpc11 is used to control the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10 ?adpc10 is used to control the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled table 9-9. apctl1 register field descriptions (continued) field description
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 135 9.3.10 pin control 3 register (apctl3) apctl3 is used to control channels 16?3 of the adc module. 1 adpc9 adc pin control 9 ?adpc9 is used to control the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8 ?adpc8 is used to control the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset: 0 0 0 0 0 0 0 0 figure 9-13. pin control 3 register (apctl3) table 9-11. apctl3 register field descriptions field description 7 adpc23 adc pin control 23 ?adpc23 is used to control the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22 ?adpc22 is used to control the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21 ?adpc21 is used to control the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20 ?adpc20 is used to control the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled 3 adpc19 adc pin control 19 ?adpc19 is used to control the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18 ?adpc18 is used to control the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled table 9-10. apctl2 register field descriptions (continued) field description
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 136 freescale semiconductor 9.4 functional description the adc module is disabled during reset or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to-digital conversion on any of the software selectable channels. the selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result. in 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is placed in the data registers (adcrh and adcrl).in 10-bit mode, the result is rounded to 10 bits and placed in adcrh and adcrl. in 8-bit mode, the result is rounded to 8 bits and placed in adcrl. the conversion complete ?g (coco) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare function is enabled by setting the acfe bit and operates in conjunction with any of the conversion modes and con?urations. 9.4.1 clock select and divide control one of four clock sources can be selected as the clock source for the adc module. this clock source is then divided by a con?urable value to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. the bus clock, which is equal to the frequency at which software is executed. this is the default selection following reset. the bus clock divided by 2. for higher bus clock rates, this allows a maximum divide by 16 of the bus clock. altclk, as de?ed for this mcu (see module section introduction). the asynchronous clock (adack) this clock is generated from a clock source within the adc module. when selected as the clock source this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selected, its frequency must fall within the speci?d frequency range for adck. if the available clocks are too slow, the adc will not perform according to speci?ations. if the available clocks 1 adpc17 adc pin control 17 ?adpc17 is used to control the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16 ?adpc16 is used to control the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled table 9-11. apctl3 register field descriptions (continued) field description
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 137 are too fast, then the clock must be divided to the appropriate frequency. this divider is speci?d by the adiv bits and can be divide-by 1, 2, 4, or 8. 9.4.2 input select and pin control the pin control registers (apctl3, apctl2, and apctl1) are used to disable the i/o port control of the pins used as analog inputs.when a pin control register bit is set, the following conditions are forced for the associated mcu pin: the output buffer is forced to its high impedance state. the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. the pullup is disabled. 9.4.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus. consult the module introduction for information on the adhwt source speci? to this mcu. when adhwt source is available and hardware trigger is enabled (adtrg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progress when a rising edge occurs, the rising edge is ignored. in continuous convert con?uration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and con?urations. 9.4.4 conversion control conversions can be performed in either 10-bit mode or 8-bit mode as determined by the mode bits. conversions can be initiated by either a software or hardware trigger. in addition, the adc module can be con?ured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value. 9.4.4.1 initiating conversions a conversion is initiated: following a write to adcsc1 (with adch bits not all 1s) if software triggered operation is selected. following a hardware trigger (adhwt) event if hardware triggered operation is selected. following the transfer of the result to the data registers when continuous conversion is enabled. if continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation, continuous conversions begin after adcsc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted.
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 138 freescale semiconductor 9.4.4.2 completing conversions a conversion is completed when the result of the conversion is transferred into the data result registers, adcrh and adcrl. this is indicated by the setting of coco. an interrupt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from overwriting previous data in adcrh and adcrl if the previous data is in the process of being read while in 10-bit mode (the adcrh register has been read but the adcrl register has not). when blocking is active, the data transfer is blocked, coco is not set, and the new result is lost. in the case of single conversions with the compare function enabled and the compare condition false, blocking has no effect and adc operation is terminated. in all other cases of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 9.4.4.3 aborting conversions any conversion in progress will be aborted when: a write to adcsc1 occurs (the current conversion will be aborted and a new conversion will be initiated, if adch are not all 1s). a write to adcsc2, adccfg, adccvh, or adccvl occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. the mcu is reset. the mcu enters stop mode with adack not enabled. when a conversion is aborted, the contents of the data registers, adcrh and adcrl, are not altered but continue to be the values transferred after the completion of the last successful conversion. in the case that the conversion was aborted by a reset, adcrh and adcrl return to their reset states. 9.4.4.4 power control the adc module remains in its idle state until a conversion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by setting adlpc. this results in a lower maximum value for f adck (see the electrical speci?ations). 9.4.4.5 total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begins. adlsmp is used to select between short and long sample times.when sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. the
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 139 result of the conversion is transferred to adcrh and adcrl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (adlsmp=0). if the bus frequency is less than 1/11th of the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for different conditions is summarized in table 9-12 . the maximum total conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is selectable by the adiclk bits, and the divide ratio is speci?d by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, then the conversion time for a single conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet adc speci?ations. table 9-12. total conversion time vs. control conditions conversion type adiclk adlsmp max total conversion time single or ?st continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or ?st continuous 10-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or ?st continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or ?st continuous 10-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles subsequent continuous 10-bit; f bus > f adck /11 xx 1 40 adck cycles 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 s x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 s
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 140 freescale semiconductor 9.4.5 automatic compare function the compare function can be con?ured to check for either an upper limit or lower limit. after the input is sampled and converted, the result is added to the twos complement of the compare value (adccvh and adccvl). when comparing to an upper limit (acfgt = 1), if the result is greater-than or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. the value generated by the addition of the conversion result and the twos complement of the compare value is transferred to adcrh and adcrl. upon completion of a conversion while the compare function is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result registers. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can be used to monitor the voltage on a channel while the mcu is in either wait or stop3 mode. the adc interrupt will wake the mcu when the compare condition is met. 9.4.6 mcu wait mode operation the wait instruction puts the mcu in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion clock source in wait is dependent on the de?ition of altclk for this mcu. consult the module introduction for information on altclk speci? to this mcu. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 9.4.7 mcu stop3 mode operation the stop instruction is used to put the mcu in a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 9.4.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of adcrh and adcrl are unaffected by stop3 mode.after exiting from stop3 mode, a software or hardware trigger is required to resume conversions.
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 141 9.4.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc continues operation during stop3 mode. for guaranteed adc operation, the mcus voltage regulator must remain active during stop3 mode. consult the module introduction for con?uration information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it continues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note it is possible for the adc module to wake the system from low power stop and cause the mcu to begin consuming run-level currents without generating a system level interrupt. to prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in section 9.4.4.2, ?ompleting conversions ) is cleared when entering stop3 and continuing adc conversions. 9.4.8 mcu stop1 and stop2 mode operation the adc module is automatically disabled when the mcu enters either stop1 or stop2 mode. all module registers contain their reset values following exit from stop1 or stop2. therefore the module must be re-enabled and re-con?ured following exit from stop1 or stop2. 9.5 initialization information this section gives an example which provides some basic direction on how a user would initialize and con?ure the adc module. the user has the ?xibility of choosing between con?uring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. refer to table 9-6 , table 9-7 , and table 9-8 for information used in this example. note hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 9.5.1 adc module initialization example 9.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the con?uration register (adccfg) to select the input clock source and the divide ratio used to generate the internal clock, adck. this register is also used for selecting sample time and low-power con?uration.
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 142 freescale semiconductor 2. update status and control register 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control register 1 (adcsc1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. the input channel on which conversions will be performed is also selected here. 9.5.1.2 pseudo ?code example in this example, the adc module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal adck clock will be derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low power (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus clock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 unimplemented or reserved, always reads zero bit 1:0 00 reserved for freescale? internal use; always write zero adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (continuous conversions disabled) bit 4:0 adch 00001 input channel 1 selected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 143 figure 9-14. initialization flowchart for example 9.6 application information this section contains information for using the adc module in applications. the adc has been designed to be integrated into a microcontroller for use in embedded control applications requiring an a/d converter. 9.6.1 external pins and routing the following sections discuss the external pins associated with the adc module and how they should be used for best results. 9.6.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) which are available as separate pins on some devices. on other devices, v ssad is shared on the same pin as the mcu digital v ss , and on others, both v ssad and v ddad are shared with the mcu digital supply pins. in these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to the same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. yes no reset initialize adc adccfg = $98 adcsc1 = $41 adcsc2 = $00 check coco=1? read adcrh then adcrl to clear coco bit continue
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 144 freescale semiconductor in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 9.6.1.2 analog reference pins in addition to the analog supplies, the adc module has connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source that is between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad . both v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current demand is a 0.1 f capacitor with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as near as possible to the package pins. resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. inductance in this path must be minimum (parasitic only). 9.6.1.3 analog input pins the external analog inputs are typically shared with digital i/o pins on mcu devices. the pin i/o control is disabled by setting the appropriate control bit in one of the pin control registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog input. this avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. also, the input buffer draws dc current when its input is not at either v dd or v ss . setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. use of 0.01 f capacitors with good high-frequency characteristics is suf?ient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to $3ff (full scale 10-bit representation) or $ff (full scale 8-bit representation). if the input is equal to or less than v refl , the converter circuit converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. there will be a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cycles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions.
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 145 9.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 9.6.2.1 sampling error for proper conversions, the input must be sampled long enough to achieve the proper accuracy. given the maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pf, sampling to within 1/4 lsb (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the resistance of the external analog source (r as ) is kept below 5 k . higher source resistances or higher-accuracy sampling is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 9.6.2.2 pin leakage error leakage on the i/o pins can cause conversion error if the external analog source resistance (r as ) is high. if this error cannot be tolerated by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bit mode or 10 in 10-bit mode). 9.6.2.3 noise-induced errors system noise which occurs during the sample or conversion process can affect the accuracy of the conversion. the adc accuracy numbers are guaranteed as speci?d only if the following conditions are met: there is a 0.1 f low-esr capacitor from v refh to v refl . there is a 0.1 f low-esr capacitor from v ddad to v ssad . if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ? ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. for software triggered conversions, immediately follow the write to the adcsc1 with a wait instruction or stop instruction. for stop3 mode operation, select adack as the clock source. operation in stop3 reduces v dd noise but increases effective conversion time due to stop recovery. there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where external system activity causes radiated or conducted noise emissions or excessive v dd noise is coupled into the adc. in these situations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this will improve noise issues but will affect sample rate based on the external analog source resistance).
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 146 freescale semiconductor average the result by converting the analog input many times in succession and dividing the sum of the results. four samples are required to eliminate the effect of a 1 lsb , one-time error. reduce the effect of synchronous noise by operating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 9.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). each step ideally has the same height (1 code) and width. the width is de?ed as the delta between the transition points to one code and the next. the ideal code width for an n bit converter (in this case n can be 8 or 10), de?ed as 1 lsb , is: 1 lsb = (v refh - v refl ) / 2 n eqn. 9-2 there is an inherent quantization error due to the digitization of the result. for 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the ?st ($000) conversion is only 1/2 lsb and the code width of the last ($ff or $3ff) is 1.5 lsb . 9.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. these errors are: zero-scale error (e zs ) (sometimes called offset) this error is de?ed as the difference between the actual code width of the ?st conversion and the ideal code width (1/2 lsb ). note, if the ?st conversion is $001, then the difference between the actual $001 code width and its ideal (1 lsb )is used. full-scale error (e fs ) ?this error is de?ed as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb ). note, if the last conversion is $3fe, then the difference between the actual $3fe code width and its ideal (1 lsb ) is used. differential non-linearity (dnl) this error is de?ed as the worst-case difference between the actual code width and the ideal code width for all conversions. integral non-linearity (inl) this error is de?ed as the highest-value the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. total unadjusted error (tue) this error is de?ed as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 9.6.2.6 code jitter, non-monotonicity and missing codes analog-to-digital converters are susceptible to three special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is in?itesimally smaller than the transition voltage, the
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 147 converter yields the lower code (and vice-versa). however, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. this range is normally around 1/2 lsb and will increase with noise. this error may be reduced by repeatedly sampling the input and averaging the result. additionally the techniques discussed in section 9.6.2.3 will reduce this error. non-monotonicity is de?ed as when, except for code jitter, the converter converts to a lower code for a higher input voltage. missing codes are those values which are never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and to have no missing codes.
chapter 9 analog-to-digital converter (s08adc10v1) mc9s08sh8 mcu series data sheet, rev. 1 148 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 149 chapter 10 internal clock source (s08icsv2) 10.1 introduction the internal clock source (ics) module provides clock source choices for the mcu. the module contains a frequency-locked loop (fll) as a clock source that is controllable by either an internal or an external reference clock. the module can provide this fll clock or either of the internal or external reference clocks as a source for the mcu system clock. there are also signals provided to control a low power oscillator (xosc) module to allow the use of an external crystal/resonator as the external reference clock. whichever clock source is chosen, it is passed through a reduced bus divider (bdiv) which allows a lower ?al output clock frequency to be derived. the bus frequency will be one-half of the icsout frequency. 10.1.1 module con?uration when the internal reference is enabled in stop mode (irefsten = 1), the voltage regulator must also be enabled in stop mode by setting the lvde and lvdse bits in the spmsc1 register. figure 10-1 shows the mc9s08sh8 block diagram with the ics highlighted.
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 150 freescale semiconductor figure 10-1. mc9s08sh8 block diagram highlighting the ics module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 151 10.1.2 features key features of the ics module follow. for device speci? information, refer to the ics characteristics in the electricals section of the documentation. frequency-locked loop (fll) is trimmable for accuracy 0.2% resolution using internal 32khz reference 2% deviation over voltage and temperature using internal 32khz reference internal or external reference clocks up to 5mhz can be used to control the fll 3 bit select for reference divider is provided internal reference clock has 9 trim bits available internal or external reference clocks can be selected as the clock source for the mcu whichever clock is selected as the source can be divided down 2 bit select for clock divider is provided allowable dividers are: 1, 2, 4, 8 bdc clock is provided as a constant divide by 2 of the dco output control signals for a low power oscillator as the external reference clock are provided hgo, range, erefs, erclken, erefsten fll engaged internal mode is automatically selected out of reset 10.1.3 block diagram figure 10-2 is the ics block diagram.
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 152 freescale semiconductor figure 10-2. internal clock source (ics) block diagram 10.1.4 modes of operation there are seven modes of operation for the ics: fei, fee, fbi, fbilp, fbe, fbelp, and stop. 10.1.4.1 fll engaged interna l (fei) in fll engaged internal mode, which is the default mode, the ics supplies a clock derived from the fll which is controlled by the internal reference clock. the bdc clock is supplied from the fll. 10.1.4.2 fll engaged external (fee) in fll engaged external mode, the ics supplies a clock derived from the fll which is controlled by an external reference clock. the bdc clock is supplied from the fll. 10.1.4.3 fll bypassed interna l (fbi) in fll bypassed internal mode, the fll is enabled and controlled by the internal reference clock, but is bypassed. the ics supplies a clock derived from the internal reference clock. the bdc clock is supplied from the fll. dco filter rdiv trim / 2 9 external reference irefs clock source block clks n=0-7 / 2 n n=0-3 / 2 n internal reference clock bdiv 9 icslclk icsout icsirclk erefs range erefsten hgo optional irefsten icserclk internal clock source block lp icsffclk erclken irclken dcoout fll rdiv_clk
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 153 10.1.4.4 fll bypassed interna l low power (fbilp) in fll bypassed internal low power mode, the fll is disabled and bypassed, and the ics supplies a clock derived from the internal reference clock. the bdc clock is not available. 10.1.4.5 fll bypassed externa l (fbe) in fll bypassed external mode, the fll is enabled and controlled by an external reference clock, but is bypassed. the ics supplies a clock derived from the external reference clock. the external reference clock can be an external crystal/resonator supplied by an osc controlled by the ics, or it can be another external clock source. the bdc clock is supplied from the fll. 10.1.4.6 fll bypassed externa l low power (fbelp) in fll bypassed external low power mode, the fll is disabled and bypassed, and the ics supplies a clock derived from the external reference clock. the external reference clock can be an external crystal/resonator supplied by an osc controlled by the ics, or it can be another external clock source. the bdc clock is not available. 10.1.4.7 stop (stop) in stop mode the fll is disabled and the internal or external reference clocks can be selected to be enabled or disabled. the bdc clock is not available and the ics does not provide an mcu clock source. 10.2 external signal description there are no ics signals that connect off chip. 10.3 register de?ition figure 10-1 is a summary of ics registers. table 10-1. ics register summary name 76543 2 1 0 icsc1 r clks rdiv irefs irclken irefsten w icsc2 r bdiv range hgo lp erefs erclken erefsten w icstrm r trim w icssc r 0 0 0 irefst clkst oscinit ftrim w
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 154 freescale semiconductor 10.3.1 ics control register 1 (icsc1) 7 654 3 210 r clks rdiv irefs irclken irefsten w reset: 0 0 0 0 0 1 0 0 figure 10-3. ics control register 1 (icsc1) table 10-2. ics control register 1 field descriptions field description 7:6 clks clock source select ?selects the clock source that controls the bus frequency. the actual bus frequency depends on the value of the bdiv bits. 00 output of fll is selected. 01 internal reference clock is selected. 10 external reference clock is selected. 11 reserved, defaults to 00. 5:3 rdiv reference divider ?selects the amount to divide down the fll reference clock selected by the irefs bits. resulting frequency must be in the range 31.25 khz to 39.0625 khz. 000 encoding 0 ?divides reference clock by 1 (reset default) 001 encoding 1 ?divides reference clock by 2 010 encoding 2 ?divides reference clock by 4 011 encoding 3 ?divides reference clock by 8 100 encoding 4 ?divides reference clock by 16 101 encoding 5 ?divides reference clock by 32 110 encoding 6 ?divides reference clock by 64 111 encoding 7 ?divides reference clock by 128 2 irefs internal reference select ?the irefs bit selects the reference clock source for the fll. 1 internal reference clock selected 0 external reference clock selected 1 irclken internal reference clock enable ?the irclken bit enables the internal reference clock for use as icsirclk. 1 icsirclk active 0 icsirclk inactive 0 irefsten internal reference stop enable ?the irefsten bit controls whether or not the internal reference clock remains enabled when the ics enters stop mode. 1 internal reference clock stays enabled in stop if irclken is set or if ics is in fei, fbi, or fbilp mode before entering stop 0 internal reference clock is disabled in stop
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 155 10.3.2 ics control register 2 (icsc2) 76543210 r bdiv range hgo lp erefs erclken erefsten w reset: 0 1 0 0 0 0 0 0 figure 10-4. ics control register 2 (icsc2) table 10-3. ics control register 2 field descriptions field description 7:6 bdiv bus frequency divider selects the amount to divide down the clock source selected by the clks bits. this controls the bus frequency. 00 encoding 0 ?divides selected clock by 1 01 encoding 1 ?divides selected clock by 2 (reset default) 10 encoding 2 ?divides selected clock by 4 11 encoding 3 ?divides selected clock by 8 5 range frequency range select ?selects the frequency range for the external oscillator. 1 high frequency range selected for the external oscillator 0 low frequency range selected for the external oscillator 4 hgo high gain oscillator select ?the hgo bit controls the external oscillator mode of operation. 1 con?ure external oscillator for high gain operation 0 con?ure external oscillator for low power operation 3 lp low power select ?the lp bit controls whether the fll is disabled in fll bypassed modes. 1 fll is disabled in bypass modes unless bdm is active 0 fll is not disabled in bypass mode 2 erefs external reference select ?the erefs bit selects the source for the external reference clock. 1 oscillator requested 0 external clock source requested 1 erclken external reference enable ?the erclken bit enables the external reference clock for use as icserclk. 1 icserclk active 0 icserclk inactive 0 erefsten external reference stop enable ?the erefsten bit controls whether or not the external reference clock remains enabled when the ics enters stop mode. 1 external reference clock stays enabled in stop if erclken is set or if ics is in fee, fbe, or fbelp mode before entering stop 0 external reference clock is disabled in stop
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 156 freescale semiconductor 10.3.3 ics trim register (icstrm) 10.3.4 ics status and control (icssc) 7 654 3 210 r trim w por: 1 0 0 0 0 0 0 0 reset: u u u u u u u u figure 10-5. ics trim register (icstrm) table 10-4. ics trim register field descriptions field description 7:0 trim ics trim setting ?the trim bits control the internal reference clock frequency by controlling the internal reference clock period. the bits?effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). increasing the binary value in trim will increase the period, and decreasing the value will decrease the period. an additional ?e trim bit is available in icssc as the ftrim bit. 7 654 3 210 r 0 0 0 irefst clkst oscinit ftrim w por: reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 u figure 10-6. ics status and control register (icssc) table 10-5. ics status and control register field descriptions field description 7:5 reserved, should be cleared. 4 irefst internal reference status the irefst bit indicates the current source for the reference clock. the irefst bit does not update immediately after a write to the irefs bit due to internal synchronization between clock domains. 0 source of reference clock is external clock. 1 source of reference clock is internal clock. 3-2 clkst clock mode status ?the clkst bits indicate the current clock mode. the clkst bits don? update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 output of fll is selected. 01 fll bypassed, internal reference clock is selected. 10 fll bypassed, external reference clock is selected. 11 reserved.
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 157 10.4 functional description 10.4.1 operational modes figure 10-7. clock switching modes the seven states of the ics are shown as a state diagram and are described below. the arrows indicate the allowed movements between the states. 10.4.1.1 fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation and is entered when all the following conditions occur: 1 osc initialization if the external reference clock is selected by erclken or by the ics being in fee, fbe, or fbelp mode, and if erefs is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. this bit is only cleared when either erclken or erefs are cleared. 0 ics fine trim ?the ftrim bit controls the smallest adjustment of the internal reference clock frequency. setting ftrim will increase the period and clearing ftrim will decrease the period by the smallest amount possible. table 10-5. ics status and control register field descriptions (continued) field description fll bypassed internal low power(fbilp) irefs=1 clks=00 entered from any state when mcu enters stop fll engaged internal (fei) fll bypassed internal (fbi) fll bypassed external (fbe) fll engaged external (fee) fll bypassed external low power(fbelp) irefs=0 clks=00 irefs=0 clks=10 bdm enabled or lp =0 returns to state that was active before mcu entered stop, unless reset occurs while in stop. irefs=0 clks=10 bdm disabled and lp=1 irefs=1 clks=01 bdm enabled or lp=0 irefs=1 clks=01 bdm disabled and lp=1 stop
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 158 freescale semiconductor clks bits are written to 00 irefs bit is written to 1 rdiv bits are written to divide trimmed reference clock to be within the range of 31.25 khz to 39.0625 khz. in fll engaged internal mode, the icsout clock is derived from the fll clock, which is controlled by the internal reference clock. the fll loop will lock the frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk is available for bdc communications, and the internal reference clock is enabled. 10.4.1.2 fll engaged external (fee) the fll engaged external (fee) mode is entered when all the following conditions occur: clks bits are written to 00 irefs bit is written to 0 rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz in fll engaged external mode, the icsout clock is derived from the fll clock which is controlled by the external reference clock.the fll loop will lock the frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk is available for bdc communications, and the external reference clock is enabled. 10.4.1.3 fll bypassed internal (fbi) the fll bypassed internal (fbi) mode is entered when all the following conditions occur: clks bits are written to 01 irefs bit is written to 1. bdm mode is active or lp bit is written to 0 in fll bypassed internal mode, the icsout clock is derived from the internal reference clock. the fll clock is controlled by the internal reference clock, and the fll loop will lock the fll frequency to 1024 times the reference frequency, as selected by the rdiv bits. the icslclk will be available for bdc communications, and the internal reference clock is enabled. 10.4.1.4 fll bypassed internal low power (fbilp) the fll bypassed internal low power (fbilp) mode is entered when all the following conditions occur: clks bits are written to 01 irefs bit is written to 1. bdm mode is not active and lp bit is written to 1 in fll bypassed internal low power mode, the icsout clock is derived from the internal reference clock and the fll is disabled. the icslclk will be not be available for bdc communications, and the internal reference clock is enabled.
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 159 10.4.1.5 fll bypassed external (fbe) the fll bypassed external (fbe) mode is entered when all the following conditions occur: clks bits are written to 10. irefs bit is written to 0. bdm mode is active or lp bit is written to 0. in fll bypassed external mode, the icsout clock is derived from the external reference clock. the fll clock is controlled by the external reference clock, and the fll loop will lock the fll frequency to 1024 times the reference frequency, as selected by the rdiv bits, so that the icslclk will be available for bdc communications, and the external reference clock is enabled. 10.4.1.6 fll bypassed external low power (fbelp) the fll bypassed external low power (fbelp) mode is entered when all the following conditions occur: clks bits are written to 10. irefs bit is written to 0. bdm mode is not active and lp bit is written to 1. in fll bypassed external low power mode, the icsout clock is derived from the external reference clock and the fll is disabled. the icslclk will be not be available for bdc communications. the external reference clock is enabled. 10.4.1.7 stop stop mode is entered whenever the mcu enters a stop state. in this mode, all ics clock signals are static except in the following cases: icsirclk will be active in stop mode when all the following conditions occur: irclken bit is written to 1 irefsten bit is written to 1 icserclk will be active in stop mode when all the following conditions occur: erclken bit is written to 1 erefsten bit is written to 1 10.4.2 mode switching when switching between fll engaged internal (fei) and fll engaged external (fee) modes the irefs bit can be changed at anytime, but the rdiv bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 khz to 39.0625 khz. after a change in the irefs value the fll will begin locking again after a few full cycles of the resulting divided reference frequency. the completion of the switch is shown by the irefst bit.
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 160 freescale semiconductor the clks bits can also be changed at anytime, but the rdiv bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 khz to 39.0625 khz. the actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. if the newly selected clock is not available, the previous clock will remain selected. 10.4.3 bus frequency divider the bdiv bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 10.4.4 low power bit usage the low power bit (lp) is provided to allow the fll to be disabled and thus conserve power when it is not being used. however, in some applications it may be desirable to enable the fll and allow it to lock for maximum accuracy before switching to an fll engaged mode. do this by writing the lp bit to 0. 10.4.5 internal reference clock when irclken is set the internal reference clock signal will be presented as icsirclk, which can be used as an additional clock source. the icsirclk frequency can be re-targeted by trimming the period of the internal reference clock. this can be done by writing a new value to the trim bits in the icstrm register. writing a larger value will slow down the icsirclk frequency, and writing a smaller value to the icstrm register will speed up the icsirclk frequency. the trim bits will effect the icsout frequency if the ics is in fll engaged internal (fei), fll bypassed internal (fbi), or fll bypassed internal low power (fbilp) mode. the trim and ftrim value will not be affected by a reset. until icsirclk is trimmed, programming low reference divider (rdiv) factors may result in icsout frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing speci?ations (see the device overview chapter). if irefsten is set and the irclken bit is written to 1, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. all mcu devices are factory programmed with a trim value in a reserved memory location. this value can be copied to the icstrm register during reset initialization. the factory trim value does not include the ftrim bit. for ?er precision, the user can trim the internal oscillator in the application and set the ftrim bit accordingly. 10.4.6 optional external reference clock the ics module can support an external reference clock with frequencies between 31.25 khz to 5 mhz in all modes. when the erclken is set, the external reference clock signal will be presented as icserclk, which can be used as an additional clock source. when irefs = 1, the external reference clock will not be used by the fll and will only be used as icserclk. in these modes, the frequency can be equal to the maximum frequency the chip-level timing speci?ations will support (see the device overview chapter).
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 161 if erefsten is set and the erclken bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 10.4.7 fixed frequency clock the ics presents the divided fll reference clock as icsffclk for use as an additional clock source for peripheral modules. the ics provides an output signal (icsffe) which indicates when the ics is providing icsout frequencies four times or greater than the divided fll reference clock (icsffclk). in fll engaged mode (fei and fee) this is always true and icsffe is always high. in ics bypass modes, icsffe will get asserted for the following combinations of bdiv and rdiv values: bdiv=00 (divide by 1), rdiv 010 bdiv=01 (divide by 2), rdiv 011 bdiv=10 (divide by 4), rdiv 100 bdiv=11 (divide by 8), rdiv 101
chapter 10 internal clock source (s08icsv2) mc9s08sh8 mcu series data sheet, rev. 1 162 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 163 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction the inter-integrated circuit (iic) provides a method of communication between a number of devices. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. note the sda and scl should not be driven above v dd . these pins are psuedo open-drain containing a protection diode to v dd . 11.1.1 module con?uration the iic module pins, sda and scl can be repositioned under software control using iicps in sopt1 as as shown in table 11-1 . iicps in sopt1 selects which general-purpose i/o ports are associated with iic operation. figure 11-1 shows the mc9s08sh8 block diagram with the iic module highlighted. table 11-1. iic position options iicps in sopt1 port pin for sda port pin for scl 0 (default) pta2 pta3 1 ptb6 ptb7
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 164 freescale semiconductor figure 11-1. mc9s08sh8 block diagram highlighting the iic module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 165 11.1.2 features the iic includes these distinctive features: compatible with iic bus standard multi-master operation software programmable for one of 64 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identi?ation interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection general call recognition 10-bit address extension 11.1.3 modes of operation a brief description of the iic in the various mcu modes is given here. run mode ?this is the basic mode of operation. to conserve power in this mode, disable the module. wait mode ?the module continues to operate while the mcu is in wait mode and can provide a wake-up interrupt. stop mode ?the iic is inactive in stop3 mode for reduced power consumption. the stop instruction does not affect iic register states. stop2 resets the register contents. 11.1.4 block diagram figure 11-2 is a block diagram of the iic.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 166 freescale semiconductor figure 11-2. iic functional block diagram 11.2 external signal description this section describes each user-accessible pin signal. 11.2.1 scl ?serial clock line the bidirectional scl is the serial clock line of the iic system. 11.2.2 sda ?serial data line the bidirectional sda is the serial data line of the iic system. 11.3 register de?ition this section consists of the iic register descriptions in address order. refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 167 freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 11.3.1 iic address register (iica) 11.3.2 iic frequency divider register (iicf) 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w reset 00000000 = unimplemented or reserved figure 11-3. iic address register (iica) table 11-2. iica field descriptions field description 7? ad[7:1] slave address. the ad[7:1] ?ld contains the slave address to be used by the iic module. this ?ld is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 76543210 r mult icr w reset 00000000 figure 11-4. iic frequency divider register (iicf)
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 168 freescale semiconductor for example, if the bus speed is 8 mhz, the table below shows the possible hold time values with different icr and mult selections to achieve an iic baud rate of 100kbps. table 11-3. iicf field descriptions field description 7? mult iic multiplier factor . the mult bits de?e the multiplier factor, mul. this factor, along with the scl divider, generates the iic baud rate. the multiplier factor mul as de?ed by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5? icr iic clock rate . the icr bits are used to prescale the bus clock for bit rate selection. these bits and the mult bits determine the iic baud rate, the sda hold time, the scl start hold time, and the scl stop hold time. table 11-5 provides the scl divider and hold values for corresponding values of the icr. the scl divider multiplied by multiplier factor mul generates iic baud rate. eqn. 11-1 sda hold time is the delay from the falling edge of scl (iic clock) to the changing of sda (iic data). sda hold time = bus period (s) mul sda hold value eqn. 11-2 scl start hold time is the delay from the falling edge of sda (iic data) while scl is high (start condition) to the falling edge of scl (iic clock). scl start hold time = bus period (s) mul scl start hold value eqn. 11-3 scl stop hold time is the delay from the rising edge of scl (iic clock) to the rising edge of sda sda (iic data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value eqn. 11-4 table 11-4. hold time values for 8 mhz bus speed mult icr hold times ( s) sda scl start scl stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0b 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 iic baud rate bus speed (hz) mul scldivider -------------------------------------------- - =
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 169 table 11-5. iic divider and hold values icr (hex) scl divider sda hold value scl hold (start) value sda hold (stop) value icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 170 freescale semiconductor 11.3.3 iic control register (iicc1) 11.3.4 iic status register (iics) 76543210 r iicen iicie mst tx txak 000 w rsta reset 00000000 = unimplemented or reserved figure 11-5. iic control register (iicc1) table 11-6. iicc1 field descriptions field description 7 iicen iic enable. the iicen bit determines whether the iic module is enabled. 0 iic is not enabled 1 iic is enabled 6 iicie iic interrupt enable. the iicie bit determines whether an iic interrupt is requested. 0 iic interrupt request not enabled 1 iic interrupt request enabled 5 mst master mode select. the mst bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 slave mode 1 master mode 4 tx transmit mode select. the tx bit selects the direction of master and slave transfers. in master mode, this bit should be set according to the type of transfer required. therefore, for address cycles, this bit is always high. when addressed as a slave, this bit should be set by software according to the srw bit in the status register. 0 receive 1 transmit 3 txak transmit acknowledge enable. this bit speci?s the value driven onto the sda during data acknowledge cycles for master and slave receivers. 0 an acknowledge signal is sent out to the bus after receiving one data byte 1 no acknowledge signal response is sent 2 rsta repeat start. writing a 1 to this bit generates a repeated start condition provided it is the current master. this bit is always read as cleared. attempting a repeat at the wrong time results in loss of arbitration. 76543210 r tcf iaas busy arbl 0srw iicif rxak w reset 10000000 = unimplemented or reserved figure 11-6. iic status register (iics)
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 171 11.3.5 iic data i/o register (iicd) table 11-7. iics field descriptions field description 7 tcf transfer complete flag. this bit is set on the completion of a byte transfer. this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iicd register in receive mode or writing to the iicd in transmit mode. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave. the iaas bit is set when the calling address matches the programmed slave address or when the gcaen bit is set and a general call is received. writing the iicc register clears this bit. 0 not addressed 1 addressed as a slave 5 busy bus busy. the busy bit indicates the status of the bus regardless of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle 1 bus is busy 4 arbl arbitration lost. this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software by writing a 1 to it. 0 standard bus operation 1 loss of arbitration 2 srw slave read/write. when addressed as a slave, the srw bit indicates the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 iicif iic interrupt flag. the iicif bit is set when an interrupt is pending. this bit must be cleared by software, by writing a 1 to it in the interrupt routine. one of the following events can set the iicif bit: one byte transfer completes match of slave address to calling address arbitration lost 0 no interrupt pending 1 interrupt pending 0 rxak receive acknowledge . when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received 1 no acknowledge received 76543210 r data w reset 00000000 figure 11-7. iic data i/o register (iicd)
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 172 freescale semiconductor note when transitioning out of master receive mode, the iic mode should be switched before reading the iicd register to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are available after an address match has occurred. the tx bit in iicc must correctly re?ct the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is con?ured for master transmit but a master receive is desired, reading the iicd does not initiate the receive. reading the iicd returns the last byte received while the iic is con?ured in master receive or slave receive modes. the iicd does not re?ct every byte transmitted on the iic bus, nor can software verify that a byte has been written to the iicd correctly by reading it back. in master transmit mode, the ?st byte of data written to iicd following assertion of mst is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required r/ w bit (in position bit 0). 11.3.6 iic control register 2 (iicc2) table 11-8. iicd field descriptions field description 7? data data in master transmit mode, when data is written to the iicd, a data transfer is initiated. the most signi?ant bit is sent ?st. in master receive mode, reading this register initiates receiving of the next byte of data. 76543210 r gcaen adext 000 ad10 ad9 ad8 w reset 00000000 = unimplemented or reserved figure 11-8. iic control register (iicc2) table 11-9. iicc2 field descriptions field description 7 gcaen general call address enable. the gcaen bit enables or disables general call address. 0 general call address is disabled 1 general call address is enabled 6 adext address extension. the adext bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2? ad[10:8] slave address. the ad[10:8] ?ld contains the upper three bits of the slave address in the 10-bit address scheme. this ?ld is only valid when the adext bit is set.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 173 11.4 functional description this section provides a complete functional description of the iic module. 11.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logic and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal slave address transmission data transfer stop signal the stop signal should not be confused with the cpu stop instruction. the iic bus system communication is described brie? in the following sections and illustrated in figure 11-9 . figure 11-9. iic bus transmission signals 11.4.1.1 start signal when the bus is free, no master device is engaging the bus (scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 11-9 , a start signal is de?ed as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 99 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit wr ite start signal start signal ack bit calling address read/ wr ite stop signal no ack bit read/ wr ite
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 174 freescale semiconductor 11.4.1.2 slave address transmission the ?st byte of data transferred immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/ w bit. the r/ w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. this is done by pulling the sda low at the ninth clock (see figure 11-9 ). no two slaves in the system may have the same address. if the iic module is the master, it must not transmit an address equal to its own slave address. the iic cannot be master and slave at the same time. however, if arbitration is lost during an address cycle, the iic reverts to slave mode and operates correctly even if it is being addressed by another master. 11.4.1.3 data transfer before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction speci?d by the r/ w bit sent by the calling master. all transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 11-9 . there is one clock pulse on scl for each data bit, the msb being transferred ?st. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at the ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the ninth bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsuccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is aborted and the master does one of two things: relinquishes the bus by generating a stop signal. commences a new calling by generating a repeated start signal. 11.4.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeated start. a stop signal is de?ed as a low-to-high transition of sda while scl at logical 1 (see figure 11-9 ). the master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 175 11.4.1.5 repeated start signal as shown in figure 11-9 , a repeated start signal is a start signal generated without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. the devices start counting their low period and after a devices clock has gone low, it holds the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 11-10 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods. the ?st device to complete its high period pulls the scl line low again. figure 11-10. iic clock synchronization scl1 scl2 scl internal counter reset delay start counting high period
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 176 freescale semiconductor 11.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 11.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 11.4.2 10-bit address for 10-bit addressing, 0x11110 is used for the ?st 5 bits of the ?st address byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed (see table 11-10 ). when a 10-bit address follows a start condition, each slave compares the ?st seven bits of the ?st byte of the slave address (11110xx) with its own address and tests whether the eighth bit (r/ w direction bit) is 0. more than one device can ?d a match and generate an acknowledge (a1). then, each slave that ?ds a match compares the eight bits of the second byte of the slave address with its own address. only one slave ?ds a match and generates an acknowledge (a2). the matching slave remains addressed by the master until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after the master-transmitter has sent the ?st byte of the 10-bit address, the slave-receiver sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.2.2 master-receiver addresses a slave-transmitter the transfer direction is changed after the second r/ w bit (see table 11-11 ). up to and including acknowledge bit a2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slave remembers that it was addressed before. this slave then checks whether the ?st seven bits of the ?st byte of the slave address following sr are the same as they were after the start condition (s) and tests whether the eighth (r/ w) bit is 1. if there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge a3. the slave-transmitter remains addressed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 data a ... data a/a p 11110 + ad10 + ad9 0 ad[8:1] table 11-10. master-transmitter addresses slave-receiver with a 10-bit address
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 177 after a repeated start condition (sr), all other slave devices also compare the ?st seven bits of the ?st byte of the slave address with their own addresses and test the eighth (r/ w) bit. however, none of them are addressed because r/ w = 1 (for 10-bit devices) or the 11110xx slave address (for 7-bit devices) does not match. after the master-receiver has sent the ?st byte of the 10-bit address, the slave-transmitter sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.3 general call address general calls can be requested in 7-bit address or 10-bit address. if the gcaen bit is set, the iic matches the general call address as well as its own slave address. when the iic responds to a general call, it acts as a slave-receiver and the iaas bit is set after the address cycle. software must read the iicd register after the ?st byte transfer to determine whether the address matches is its own slave address or a general call. if the value is 00, the match is a general call. if the gcaen bit is clear, the iic ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 11.6 interrupts the iic generates a single interrupt. an interrupt from the iic is generated when any of the events in table 11-12 occur, provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by software by writing a 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. 11.6.1 byte transfer interrupt the tcf (transfer complete ?g) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 sr slave address 1st 7 bits r/w a3 data a ... data a p 11110 + ad10 + ad9 0 ad[8:1] 11110 + ad10 + ad9 1 table 11-11. master-receiver addresses a slave-transmitter with a 10-bit address table 11-12. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 178 freescale semiconductor 11.6.2 address detect interrupt when the calling address matches the programmed slave address (iic address register) or when the gcaen bit is set and a general call is received, the iaas bit in the status register is set. the cpu is interrupted, provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 11.6.3 arbitration lost interrupt the iic is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt when it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in the following circumstances: sda sampled as a low when the master drives a high during an address or data transmit cycle. sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected when the master did not request it. this bit must be cleared by software writing a 1 to it.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 179 11.7 initialization/application information figure 11-11. iic module quick start module initialization (slave) 1. write: iicc2 to enable or disable general call to select 10-bit or 7-bit addressing mode 2. write: iica to set the slave address 3. write: iicc1 to enable iic and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in figure 11-12 module initialization (master) 1. write: iicf to set the iic baud rate (example provided in this chapter) 2. write: iicc1 to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 11-12 5. write: iicc1 to enable tx 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc1 iicen iicie mst module con?uration arbl 0 srw iicif rxak iics tcf iaas busy module status ?gs register model ad[7:1] when addressed as a slave (in slave mode), the module responds to this address mult icr iicd data data register; write to transmit iic data read to read iic data 0 ad10 ad9 ad8 iicc2 gcaen adext address con?uration 0 0
chapter 11 inter-integrated circuit (s08iicv2) mc9s08sh8 mcu series data sheet, rev. 1 180 freescale semiconductor figure 11-12. typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0) see note 1 notes: 1. if general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). if the received address was a general call address, then the general call must be handled by user software. 2. when 10-bit addressing is used to address a slave, the slave sees an interrupt following the ?st byte of the extended address. see note 2
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 181 chapter 12 modulo timer (s08mtimv1) 12.1 introduction the mtim is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. the central component of the mtim is the 8-bit counter, which can operate as a free-running counter or a modulo counter. a timer over?w interrupt can be enabled to generate periodic interrupts for time-based software loops. figure 12-1 shows the mc9s08sh8 block diagram with the mtim module highlighted. 12.1.1 mtim con?uration information the external clock for the mtim module, tclk, is selected by setting clks = 1:1 or 1:0 in mtimclk, which selects the tclk pin input. the tclk input on pta0 can be enabled as external clock inputs to both mtim and tpm modules simultaneously.
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 182 freescale semiconductor figure 12-1. mc9s08sh8 block diagram highlighting the mtim module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 183 12.1.2 features timer system features include: 8-bit up-counter free-running or 8-bit modulo limit software controllable interrupt on over?w counter reset bit (trst) counter stop bit (tstp) four software selectable clock sources for input to prescaler: system bus clock ?rising edge fixed frequency clock (xclk) ?rising edge external clock source on the tclk pin ?rising edge external clock source on the tclk pin ?falling edge nine selectable clock prescale values: clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 12.1.3 modes of operation this section de?es the mtims operation in stop, wait and background debug modes. 12.1.3.1 mtim in wait mode the mtim continues to run in wait mode if enabled before executing the wait instruction. therefore, the mtim can be used to bring the mcu out of wait mode if the timer over?w interrupt is enabled. for lowest possible current consumption, the mtim should be stopped by software if not needed as an interrupt source during wait mode. 12.1.3.2 mtim in stop modes the mtim is disabled in all stop modes, regardless of the settings before executing the stop instruction. therefore, the mtim cannot be used as a wake up source from stop modes. waking from stop1 and stop2 modes, the mtim will be put into its reset state. if stop3 is exited with a reset, the mtim will be put into its reset state. if stop3 is exited with an interrupt, the mtim continues from the state it was in when stop3 was entered. if the counter was active upon entering stop3, the count will resume from the current value. 12.1.3.3 mtim in active background mode the mtim suspends all counting until the microcontroller returns to normal user operating mode. counting resumes from the suspended value as long as an mtim reset did not occur (trst written to a 1 or mtim mod written).
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 184 freescale semiconductor 12.1.4 block diagram the block diagram for the modulo timer module is shown figure 12-2 . figure 12-2. modulo timer (mtim) block diagram 12.2 external signal description the mtim includes one external signal, tclk, used to input an external clock when selected as the mtim clock source. the signal properties of tclk are shown in table 12-1 . the tclk input must be synchronized by the bus clock. also, variations in duty cycle and clock jitter must be accommodated. therefore, the tclk signal must be limited to one-fourth of the bus frequency. the tclk pin can be muxed with a general-purpose port pin. see the pins and connections chapter for the pin location and priority of this function. table 12-1. signal properties signal function i/o tclk external clock source input into mtim i busclk tclk sync clock source select prescale and select divide by 8-bit counter (mtimcnt) 8-bit modulo (mtimmod) 8-bit comparator trst tstp clks ps xclk toie mtim interrupt request tof
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 185 12.3 register de?ition figure 12-3 is a summary of mtim registers. each mtim includes four registers: an 8-bit status and control register an 8-bit clock con?uration register an 8-bit counter register an 8-bit modulo register refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all mtim registers.this section refers to registers and control bits only by their names and relative address offsets. some mcus may have more than one mtim, so register names include placeholder characters to identify which mtim is being referenced. name 76543210 mtimsc rtof toie 0 tstp 0000 w trst mtimclk r0 0 clks ps w mtimcnt r count w mtimmod r mod w figure 12-3. mtim register summary
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 186 freescale semiconductor 12.3.1 mtim status and control register (mtimsc) mtim sc contains the over?w status ?g and control bits which are used to con?ure the interrupt enable, reset the counter, and stop the counter. 7 654 3 210 r tof toie 0 tstp 0 000 w trst reset: 0 0 0 1 0 0 0 0 figure 12-4. mtim status and control register table 12-2. mtim status and control register field descriptions field description 7 tof mtim over?w flag this read-only bit is set when the mtim counter register over?ws to $00 after reaching the value in the mtim modulo register. clear tof by reading the mtimsc register while tof is set, then writing a 0 to tof. tof is also cleared when trst is written to a 1 or when any value is written to the mtimmod register. 0 mtim counter has not reached the over?w value in the mtim modulo register. 1 mtim counter has reached the over?w value in the mtim modulo register. 6 toie mtim over?w interrupt enable this read/write bit enables mtim over?w interrupts. if toie is set, then an interrupt is generated when tof = 1. reset clears toie. do not set toie if tof = 1. clear tof ?st, then set toie. 0 tof interrupts are disabled. use software polling. 1 tof interrupts are enabled. 5 trst mtim counter reset when a 1 is written to this write-only bit, the mtim counter register resets to $00 and tof is cleared. reading this bit always returns 0. 0 no effect. mtim counter remains at current state. 1 mtim counter is reset to $00. 4 tstp mtim counter stop when set, this read/write bit stops the mtim counter at its current value. counting resumes from the current value when tstp is cleared. reset sets tstp to prevent the mtim from counting. 0 mtim counter is active. 1 mtim counter is stopped. 3:0 unused register bits, always read 0.
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 187 12.3.2 mtim clock con?uration register (mtimclk) mtimclk contains the clock select bits (clks) and the prescaler select bits (ps). 7 654 3 210 r 0 0 clks ps w reset: 0 0 0 0 0 0 0 0 figure 12-5. mtim clock con?uration register table 12-3. mtim clock con?uration register field description field description 7:6 unused register bits, always read 0. 5:4 clks clock source select ?these two read/write bits select one of four different clock sources as the input to the mtim prescaler. changing the clock source while the counter is active does not clear the counter. the count continues with the new clock source. reset clears clks to 000. 00 encoding 0. bus clock (busclk) 01 encoding 1. fixed-frequency clock (xclk) 10 encoding 3. external source (tclk pin), falling edge 11 encoding 4. external source (tclk pin), rising edge all other encodings default to the bus clock (busclk). 3:0 ps clock source prescaler ?these four read/write bits select one of nine outputs from the 8-bit prescaler. changing the prescaler value while the counter is active does not clear the counter. the count continues with the new prescaler value. reset clears ps to 0000. 0000 encoding 0. mtim clock source 1 0001 encoding 1. mtim clock source 2 0010 encoding 2. mtim clock source 4 0011 encoding 3. mtim clock source 8 0100 encoding 4. mtim clock source 16 0101 encoding 5. mtim clock source 32 0110 encoding 6. mtim clock source 64 0111 encoding 7. mtim clock source 128 1000 encoding 8. mtim clock source 256 all other encodings default to mtim clock source 256.
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 188 freescale semiconductor 12.3.3 mtim counter register (mtimcnt) mtim cnt is the read-only value of the current mtim count of the 8-bit counter. 12.3.4 mtim modulo register (mtimmod) 7 654 3 210 r count w reset: 0 0 0 0 0 0 0 0 figure 12-6. mtim counter register table 12-4. mtim counter register field description field description 7:0 count mtim count these eight read-only bits contain the current value of the 8-bit counter. writes have no effect to this register. reset clears the count to $00. 7 654 3 210 r mod w reset: 0 0 0 0 0 0 0 0 figure 12-7. mtim modulo register table 12-5. mtim modulo register field descriptions field description 7:0 mod mtim modulo these eight read/write bits contain the modulo value used to reset the count and set tof. a value of $00 puts the mtim in free-running mode. writing to mtimmod resets the count to $00 and clears tof. reset sets the modulo to $00.
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 189 12.4 functional description the mtim is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. the module also contains software selectable interrupt logic. the mtim counter ( mtim cnt) has three modes of operation: stopped, free-running, and modulo. out of reset, the counter is stopped. if the counter is started without writing a new value to the modulo register, then the counter will be in free-running mode. the counter is in modulo mode when a value other than $00 is in the modulo register while the counter is running. after any mcu reset, the counter is stopped and reset to $00, and the modulus is set to $00. the bus clock is selected as the default clock source and the prescale value is divide by 1. to start the mtim in free-running mode, simply write to the mtim status and control register ( mtim sc) and clear the mtim stop bit (tstp). four clock sources are software selectable: the internal bus clock, the ?ed frequency clock (xclk), and an external clock on the tclk pin, selectable as incrementing on either rising or falling edges. the mtim clock select bits (clks1:clks0) in mtim sc are used to select the desired clock source. if the counter is active (tstp = 0) when a new clock source is selected, the counter will continue counting from the previous value using the new clock source. nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32, 64, 128, or 256. the prescaler select bits (ps[3:0]) in mtim sc select the desired prescale value. if the counter is active (tstp = 0) when a new prescaler value is selected, the counter will continue counting from the previous value using the new prescaler value. the mtim modulo register ( mtim mod) allows the over?w compare value to be set to any value from $01 to $ff. reset clears the modulo value to $00, which results in a free running counter. when the counter is active (tstp = 0), the counter increments at the selected rate until the count matches the modulo value. when these values match, the counter over?ws to $00 and continues counting. the mtim over?w ?g (tof) is set whenever the counter over?ws. the ?g sets on the transition from the modulo value to $00. writing to mtim mod while the counter is active resets the counter to $00 and clears tof. clearing tof is a two-step process. the ?st step is to read the mtim sc register while tof is set. the second step is to write a 0 to tof. if another over?w occurs between the ?st and second steps, the clearing process is reset and tof will remain set after the second step is performed. this will prevent the second occurrence from being missed. tof is also cleared when a 1 is written to trst or when any value is written to the mtim mod register. the mtim allows for an optional interrupt to be generated whenever tof is set. to enable the mtim over?w interrupt, set the mtim over?w interrupt enable bit (toie) in mtim sc. toie should never be written to a 1 while tof = 1. instead, tof should be cleared ?st, then the toie can be set to 1.
chapter 12 modulo timer (s08mtimv1) mc9s08sh8 mcu series data sheet, rev. 1 190 freescale semiconductor 12.4.1 mtim operation example this section shows an example of the mtim operation as the counter reaches a matching value from the modulo register. figure 12-8. mtim counter over?w example in the example of figure 12-8 , the selected clock source could be any of the ve possible choices. the prescaler is set to ps = %0010 or divide-by-4. the modulo value in the mtim mod register is set to $aa. when the counter, mtim cnt, reaches the modulo value of $aa, the counter over?ws to $00 and continues counting. the timer over?w ?g, tof, sets when the counter value changes from $aa to $00. an mtim over?w interrupt is generated when tof is set, if toie = 1. selected clock source mtimcnt mtim clock (ps=%0010) mtimmod: $aa $a7 $a8 $a9 $aa $00 $01 tof
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 191 chapter 13 real-time counter (s08rtcv1) 13.1 introduction the rtc module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. this module can be used for time-of-day, calendar or any task scheduling functions. it can also serve as a cyclic wake up from low power modes without the need of external components.
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 192 freescale semiconductor figure 13-1. mc9s08sh8 block diagram highlighting the rtc module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 193 13.1.1 features features of the rtc module include: 8-bit up-counter 8-bit modulo match limit software controllable periodic interrupt on match three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values 1-khz internal low-power oscillator (lpo) external clock (erclk) 32-khz internal clock (irclk) 13.1.2 modes of operation this section de?es the operation in stop, wait and background debug modes. 13.1.2.1 wait mode the rtc continues to run in wait mode if enabled before executing the appropriate instruction. therefore, the rtc can bring the mcu out of wait mode if the real-time interrupt is enabled. for lowest possible current consumption, the rtc should be stopped by software if not needed as an interrupt source during wait mode. 13.1.2.2 stop modes the rtc continues to run in stop2 or stop3 mode if the rtc is enabled before executing the stop instruction. therefore, the rtc can bring the mcu out of stop modes with no external components, if the real-time interrupt is enabled. the lpo clock can be used in stop2 and stop3 modes. erclk and irclk clocks are only available in stop3 mode. power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the mcu from stop modes. 13.1.2.3 active background mode the rtc suspends all counting during active background mode until the microcontroller returns to normal user operating mode. counting resumes from the suspended value as long as the rtcmod register is not written and the rtcps and rtclks bits are not altered.
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 194 freescale semiconductor 13.1.3 block diagram the block diagram for the rtc module is shown in figure 13-2 . figure 13-2. real-time counter (rtc) block diagram 13.2 external signal description the rtc does not include any off-chip signals. 13.3 register de?ition the rtc includes a status and control register, an 8-bit counter register, and an 8-bit modulo register. refer to the direct-page register summary in the memory section of this document for the absolute address assignments for all rtc registers.this section refers to registers and control bits only by their names and relative address offsets. table 13-1 is a summary of rtc registers. table 13-1. rtc register summary name 765 4 3210 rtcsc r rtif rtclks rtie rtcps w rtccnt r rtccnt w rtcmod r rtcmod w clock source select prescaler divide-by 8-bit counter (rtccnt) 8-bit modulo (rtcmod) 8-bit comparator rtif rtie background v dd rtc interrupt request d q r e lpo rtc clock mode erclk irclk rtclks write 1 to rtif rtcps rtclks[0]
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 195 13.3.1 rtc status and control register (rtcsc) rtcsc contains the real-time interrupt status ?g (rtif), the clock select bits (rtclks), the real-time interrupt enable bit (rtie), and the prescaler select bits (rtcps). 7 654 3 210 r rtif rtclks rtie rtcps w reset: 0 0 0 0 0 0 0 0 figure 13-3. rtc status and control register (rtcsc) table 13-2. rtcsc field descriptions field description 7 rtif real-time interrupt flag this status bit indicates the rtc counter register reached the value in the rtc modulo register. writing a logic 0 has no effect. writing a logic 1 clears the bit and the real-time interrupt request. reset clears rtif. 0 rtc counter has not reached the value in the rtc modulo register. 1 rtc counter has reached the value in the rtc modulo register. 6 5 rtclks real-time clock source select. these two read/write bits select the clock source input to the rtc prescaler. changing the clock source clears the prescaler and rtccnt counters. when selecting a clock source, ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the rtc. reset clears rtclks. 00 real-time clock source is the 1-khz low power oscillator (lpo) 01 real-time clock source is the external clock (erclk) 1x real-time clock source is the internal clock (irclk) 4 rtie real-time interrupt enable. this read/write bit enables real-time interrupts. if rtie is set, then an interrupt is generated when rtif is set. reset clears rtie. 0 real-time interrupt requests are disabled. use software polling. 1 real-time interrupt requests are enabled. 3? rtcps real-time clock prescaler select. these four read/write bits select binary-based or decimal-based divide-by values for the clock source. see table 13-3 . changing the prescaler value clears the prescaler and rtccnt counters. reset clears rtcps. table 13-3. rtc prescaler divide-by values rtclks[0] rtcps 01 2 3 45678 9 101112131415 0 off 2 3 2 5 2 6 2 7 2 8 2 9 2 10 12 2 2 10 2 4 10 2 5x10 2 10 3 1 off 2 10 2 11 2 12 2 13 2 14 2 15 2 16 10 3 2x10 3 5x10 3 10 4 2x10 4 5x10 4 10 5 2x10 5
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 196 freescale semiconductor 13.3.2 rtc counter register (rtccnt) rtccnt is the read-only value of the current rtc count of the 8-bit counter. 13.3.3 rtc modulo register (rtcmod) 13.4 functional description the rtc is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. the module also contains software selectable interrupt logic. after any mcu reset, the counter is stopped and reset to 0x00, the modulus register is set to 0x00, and the prescaler is off. the 1-khz internal oscillator clock is selected as the default clock source. to start the prescaler, write any value other than zero to the prescaler select bits (rtcps). three clock sources are software selectable: the low power oscillator clock (lpo), the external clock (erclk), and the internal clock (irclk). the rtc clock select bits (rtclks) select the desired clock source. if a different value is written to rtclks, the prescaler and rtccnt counters are reset to 0x00. 7 654 3 210 r rtccnt w reset: 0 0 0 0 0 0 0 0 figure 13-4. rtc counter register (rtccnt) table 13-4. rtccnt field descriptions field description 7:0 rtccnt rtc count. these eight read-only bits contain the current value of the 8-bit counter. writes have no effect to this register. reset, writing to rtcmod, or writing different values to rtclks and rtcps clear the count to 0x00. 7 654 3 210 r rtcmod w reset: 0 0 0 0 0 0 0 0 figure 13-5. rtc modulo register (rtcmod) table 13-5. rtcmod field descriptions field description 7:0 rtcmod rtc modulo. these eight read/write bits contain the modulo value used to reset the count to 0x00 upon a compare match and set the rtif status bit. a value of 0x00 sets the rtif bit on each rising edge of the prescaler output. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. reset sets the modulo to 0x00.
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 197 rtcps and the rtclks[0] bit select the desired divide-by value. if a different value is written to rtcps, the prescaler and rtccnt counters are reset to 0x00. table 13-6 shows different prescaler period values. the rtc modulo register (rtcmod) allows the compare value to be set to any value from 0x00 to 0xff. when the counter is active, the counter increments at the selected rate until the count matches the modulo value. when these values match, the counter resets to 0x00 and continues counting. the real-time interrupt ?g (rtif) is set when a match occurs. the ?g sets on the transition from the modulo value to 0x00. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. the rtc allows for an interrupt to be generated when rtif is set. to enable the real-time interrupt, set the real-time interrupt enable bit (rtie) in rtcsc. rtif is cleared by writing a 1 to rtif. 13.4.1 rtc operation example this section shows an example of the rtc operation as the counter reaches a matching value from the modulo register. table 13-6. prescaler period rtcps 1-khz internal clock (rtclks = 00) 1-mhz external clock (rtclks = 01) 32-khz internal clock (rtclks = 10) 32-khz internal clock (rtclks = 11) 0000 off off off off 0001 8 ms 1.024 ms 250 s 32 ms 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25 s 31.25 ms 1001 2 ms 2 ms 62.5 s 62.5 ms 1010 4 ms 5 ms 125 s 156.25 ms 1011 10 ms 10 ms 312.5 s 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 198 freescale semiconductor figure 13-6. rtc counter over?w example in the example of figure 13-6 , the selected clock source is the 1-khz internal oscillator clock source. the prescaler (rtcps) is set to 0xa or divide-by-4. the modulo value in the rtcmod register is set to 0x55. when the counter, rtccnt, reaches the modulo value of 0x55, the counter over?ws to 0x00 and continues counting. the real-time interrupt ?g, rtif, sets when the counter value changes from 0x55 to 0x00. a real-time interrupt is generated when rtif is set, if rtie is set. 13.5 initialization/application information this section provides example code to give some basic direction to a user on how to initialize and con?ure the rtc module. the example software is implemented in c language. the example below shows how to implement time of day with the rtc using the 1-khz clock source to achieve the lowest possible power consumption. because the 1-khz clock source is not as accurate as a crystal, software can be added for any adjustments. for accuracy without adjustments at the expense of additional power consumption, the external clock (erclk) or the internal clock (irclk) can be selected with appropriate prescaler and modulo values. /* initialize the elapsed time counters */ seconds = 0; minutes = 0; hours = 0; days=0; /* configure rtc to interrupt every 1 second from 1-khz clock source */ rtcmod.byte = 0x00; rtcsc.byte = 0x1f; /********************************************************************** function name : rtc_isr notes : interrupt service routine for rtc module. **********************************************************************/ 0x55 0x55 0x54 0x53 0x52 0x00 0x01 rtcmod rtif rtccnt rtc clock (rtcps = 0xa) internal 1-khz clock source
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 199 #pragma trap_proc void rtc_isr(void) { /* clear the interrupt flag */ rtcsc.byte = rtcsc.byte | 0x80; /* rtc interrupts every 1 second */ seconds++; /* 60 seconds in a minute */ if (seconds > 59){ minutes++; seconds = 0; } /* 60 minutes in an hour */ if (minutes > 59){ hours++; minutes = 0; } /* 24 hours in a day */ if (hours > 23){ days ++; hours = 0; }
chapter 13 real-time counter (s08rtcv1) mc9s08sh8 mcu series data sheet, rev. 1 200 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 201 chapter 14 serial communications interface (s08sciv4) 14.1 introduction figure 14-1 shows the mc9s08sh8 block diagram with the sci module highlighted.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 202 freescale semiconductor figure 14-1. mc9s08sh8 block diagram highlighting the sci module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 203 14.1.1 features features of sci module include: full-duplex, standard non-return-to-zero (nrz) format double-buffered transmitter and receiver with separate enables programmable baud rates (13-bit modulo divider) interrupt-driven or polled operation: transmit data register empty and transmission complete receive data register full receive overrun, parity error, framing error, and noise error idle receiver detect active edge on receive pin break detect supporting lin hardware parity generation and checking programmable 8-bit or 9-bit character length receiver wakeup by idle-line or address-mark optional 13-bit break character generation / 11-bit break character detection selectable transmitter output polarity 14.1.2 modes of operation see section 14.3, ?unctional description ,?for details concerning sci operation in these modes: 8- and 9-bit data modes stop mode operation loop mode single-wire mode
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 204 freescale semiconductor 14.1.3 block diagram figure 14-2 shows the transmitter portion of the sci. figure 14-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ?tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd txinv brk13
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 205 figure 14-3 shows the receiver portion of the sci. figure 14-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ?rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 206 freescale semiconductor 14.2 register de?ition the sci has eight 8-bit registers to control baud rate, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 14.2.1 sci baud rate registers (scixbdh, scixbdl) this pair of registers controls the prescale divisor for sci baud rate generation. to update the 13-bit baud rate setting [sbr12:sbr0], ?st write to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate generator remains disabled until the ?st time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 00000000 = unimplemented or reserved figure 14-4. sci baud rate register (scixbdh) table 14-1. scixbdh field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif ?g is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif ?g is 1. 4:0 sbr[12:8] baud rate modulo divisor ?the 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in table 14-2 .
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 207 14.2.2 sci control register 1 (scixc1) this read/write register is used to control various optional features of the sci system. 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 00000100 figure 14-5. sci baud rate register (scixbdl) table 14-2. scixbdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ?these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in table 14-1 . 76543210 r loops sciswai rsrc m wake ilt pe pt w reset 00000000 figure 14-6. sci control register 1 (scixc1) table 14-3. scixc1 field descriptions field description 7 loops loop mode select ?selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ?rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci can be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ?this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connected to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ?start + 8 data bits (lsb ?st) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb ?st) + 9th data bit + stop.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 208 freescale semiconductor 14.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 3 wake receiver wakeup method select ?refer to section 14.3.3.2, ?eceiver wakeup operation ?for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ?setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 14.3.3.2.1, ?dle-line wakeup ?for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable enables hardware parity generation and checking. when parity is enabled, the most signi?ant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bit, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity. 76543210 r tie tcie rie ilie te re rwu sbk w reset 00000000 figure 14-7. sci control register 2 (scixc2) table 14-4. scixc2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre ?g is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc ?g is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf ?g is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle ?g is 1. table 14-3. scixc1 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 209 14.2.4 sci status register 1 (scixs1) this register has eight read-only status ?gs. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status ?gs. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is con?ured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traf? on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 14.3.2.1, ?end break and queued idle ?for more details. when te is written to 0, the transmitter keeps control of the port txd pin until any data, queued idle, or queued break character ?ishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ?when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wakeup control ?this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most signi?ant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 14.3.3.2, ?eceiver wakeup operation ?for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to section 14.3.2.1, ?end break and queued idle ?for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w reset 11000000 = unimplemented or reserved figure 14-8. sci status register 1 (scixs1) table 14-4. scixc2 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 210 freescale semiconductor table 14-5. scixs1 field descriptions field description 7 tdre transmit data register empty flag tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ?tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmission activity complete). tc is cleared automatically by reading scixs1 with tc = 1 and then doing one of the following three things: write to the sci data register (scixd) to transmit new data queue a preamble by changing te from 0 to 1 queue a break character by writing 1 to sbk in scixc2 5 rdrf receive data register full flag rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ?idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn? start counting idle bit times until after the stop bit. so the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost because there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if any of these samples disagrees with the rest of the samples within any bit time in the frame, the ?g nf will be set at the same time as the ?g rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 211 14.2.5 sci status register 2 (scixs2) this register has one read-only status ?g. 1 fe framing error flag fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ?pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. 76543210 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w reset 00000000 = unimplemented or reserved figure 14-9. sci status register 2 (scixs2) table 14-6. scixs2 field descriptions field description 7 lbkdif lin break detect interrupt flag lbkdif is set when the lin break detect circuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ??to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ?rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ??to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv 1 receive data inversion ?setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect rwuid controls whether the idle character that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is transmitted with length of 10 bit times (11 if m = 1) 1 break character is transmitted with length of 13 bit times (14 if m = 1) table 14-5. scixs1 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 212 freescale semiconductor when using an internal oscillator in a lin system, it is necessary to raise the break detection threshold by one bit time. under the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. this would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 14.2.6 sci control register 3 (scixc3) 1 lbkde lin break detection enable ?lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data register full (rdrf) ?gs are prevented from setting. 0 break character is detected at length of 10 bit times (11 if m = 1). 1 break character is detected at length of 11 bit times (12 if m = 1). 0 raf receiver active flag raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status ?g can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 1 setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. 76543210 rr8 t8 txdir txinv orie neie feie peie w reset 00000000 = unimplemented or reserved figure 14-10. sci control register 3 (scixc3) table 14-7. scixc3 field descriptions field description 7 r8 ninth data bit for receiver ?when the sci is con?ured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd completes automatic ?g clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter when the sci is con?ured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd register. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ?when the sci is con?ured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines the direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. table 14-6. scixs2 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 213 14.2.7 sci data register (scixd) this register is actually two separate registers. reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and writes of this register are also involved in the automatic ?g clearing mechanisms for the sci status ?gs. 14.3 functional description the sci allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the sci comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver operate independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following describes each of the blocks of the sci. 14.3.1 baud rate generation as shown in figure 14-12 , the clock source for the sci baud rate generator is the bus-rate clock. 4 txinv 1 transmit data inversion ?setting this bit reverses the polarity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ?this bit enables the overrun ?g (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ?this bit enables the noise ?g (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ?this bit enables the framing error ?g (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ?this bit enables the parity error ?g (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 1 setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. 76543210 rr 7r 6r 5r 4r 3r 2r 1r 0 wt 7t 6t 5t 4t 3t 2t 1t 0 reset 00000000 figure 14-11. sci data register (scixd) table 14-7. scixc3 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 214 freescale semiconductor figure 14-12. sci baud rate generation sci communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format and about 4 percent for 9-bit data format. although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 14.3.2 transmitter functional description this section describes the overall block diagram for the sci transmitter, as well as specialized functions for sending break and idle characters. the transmitter block diagram is shown in figure 14-2 . the transmitter output (txd) idle state defaults to logic high (txinv = 0 following reset). the transmitter output is inverted by setting txinv = 1. the transmitter is enabled by setting the te bit in scixc2. this queues a preamble character that is one full character frame of the idle state. the transmitter then remains idle until data is available in the transmit data buffer. programs store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for the remainder of this section, we will assume m = 0, selecting the normal 8-bit data mode. in 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (tdre) status ?g is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in the transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit complete ?g and enters an idle mode, with txd high, waiting for more characters to transmit. sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 215 writing 0 to te does not immediately release the pin to be a general-purpose i/o pin. any transmit activity that is in progress must ?st be completed. this includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer break of 13 bit times can be enabled by setting brk13 = 1. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is available. if sbk is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the te bit. this action queues an idle character to be sent as soon as the shifter is available. as long as the character in the shifter does not ?ish while te = 0, the sci transmitter never actually releases control of the txd pin. if there is a possibility of the shifter ?ishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 14.3.3 receiver functional description in this section, the receiver block diagram ( figure 14-3 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruct receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb ?st), and a stop bit of logic 1. for information about 9-bit data mode, refer to section 14.3.5.1, ?- and 9-bit data modes . for the remainder of this discussion, we assume the sci is con?ured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (rdrf) status table 14-8. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 216 freescale semiconductor ?g is set. if rdrf was already set indicating the receive data register (buffer) was already full, the overrun (or) status ?g is set and the new data is lost. because the sci receiver is double-buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf ?g is cleared automatically by a 2-step sequence which is normally satis?d in the course of the users program that handles receive data. refer to section 14.3.4, ?nterrupts and status flags?for more details about ?g clearing. 14.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is de?ed as a logic 0 sample after three consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a falling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit and not merely noise. if at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. the receiver then samples each bit time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in the case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise ?g (nf) will be set when the received character is transferred to the receive data buffer. the falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. in the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is ?led with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error ?g is cleared. the receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if fe is still set. 14.3.3.2 receiver wakeup operation receiver wakeup is a hardware mechanism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the ?st character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu bit is set, the status ?gs associated with the receiver (with the exception of the idle bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 217 message characters. at the end of a message, or at the beginning of the next message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the ?st character(s) of the next message. 14.3.3.2.1 idle-line wakeup when wake = 0, the receiver is con?ured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detects a full character time of the idle-line level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). when rwu is one and rwuid is zero, the idle condition that wakes up the receiver does not set the idle ?g. the receiver wakes up and waits for the ?st data character of the next message which will set the rdrf ?g and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle ?g and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit selects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 address-mark wakeup when wake = 1, the receiver is con?ured for address-mark wakeup. in this mode, rwu is cleared automatically when the receiver detects a logic 1 in the most signi?ant bit of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf ?g. in this case the character with the msb set is received even though the receiver was sleeping during most of this character time. 14.3.4 interrupts and status flags the sci system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. one interrupt vector is associated with the transmitter for tdre and tc events. another interrupt vector is associated with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separately masked by local interrupt enable masks. the ?gs can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. the sci transmitter has two status ?gs that optionally can generate hardware interrupt requests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (tc) indicates that the transmitter is ?ished transmitting all data, preamble, and break characters and is idle with txd at the inactive level. this ?g is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a hardware interrupt will be requested whenever tc = 1.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 218 freescale semiconductor instead of hardware interrupts, software polling may be used to monitor the tdre and tc status ?gs if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf ?g is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally satis?d in the normal course of the user program. if hardware interrupts are used, scixs1 must be read in the interrupt service routine (isr). normally, this is done in the isr anyway to check for receive errors, so the sequence is automatically satis?d. the idle status ?g includes logic that prevents it from getting set repeatedly when the rxd line remains idle for an extended period of time. idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error ?gs noise ?g (nf), framing error (fe), and parity error ?g (pf) get set at the same time as rdrf. these ?gs are not set in overrun cases. if rdrf was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (or) ?g gets set instead the data along with any associated nf, fe, or pf condition is lost. at any time, an active edge on the rxd serial data input pin causes the rxedgif flag to set. the rxedgif ?g is cleared by writing a ? to it. this function does depend on the receiver being enabled (re = 1). 14.3.5 additional sci functions the following sections describe additional sci functions. 14.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be con?ured to operate in 9-bit data mode by setting the m control bit in scixc1. in 9-bit mode, there is a ninth data bit to the left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 219 14.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci register data is lost and must be re-initialized upon recovery from these two stop modes. no sci module registers are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2.. an active edge on the receive input brings the cpu out of stop3 mode if the interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software should ensure stop mode is not entered while there is a character being transmitted out of or received into the sci module. 14.3.5.3 loop mode when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 14.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). single-wire mode is used to implement a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the txdir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmitter is temporarily disconnected from the txd pin so an external device can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
chapter 14 serial communications interface (s08sciv4) mc9s08sh8 mcu series data sheet, rev. 1 220 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 221 chapter 15 serial peripheral interface (s08spiv3) 15.1 introduction figure 15-1 shows the mc9s08sh8 block diagram with the spi module highlighted.
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 222 freescale semiconductor figure 15-1. mc9s08sh8 block diagram highlighting the spi module ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 223 15.1.1 features features of the spi module include: master or slave mode operation full-duplex or single-wire bidirectional option programmable transmit bit rate double-buffered transmit and receive serial clock phase and polarity options slave select output selectable msb-?st or lsb-?st shifting 15.1.2 block diagrams this section includes block diagrams showing spi system connections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 15.1.2.1 spi system block diagram figure 15-2 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master shifts data out (on the mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input ( ss pin). in this system, the master device has con?ured its ss pin as an optional slave select output. figure 15-2. spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 224 freescale semiconductor the most common uses of the spi system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial a/d or d/a converters. although figure 15-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transferred from the master mcu to a slave or from a slave to the master mcu. 15.1.2.2 spi module block diagram figure 15-3 is a block diagram of the spi module. the central element of the spi is the spi shift register. data is written to the double-buffered transmitter (write to spid) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spid). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is con?ured as a master, the clock output is routed to the spsck pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is con?ured as a slave, the spsck pin is routed to the clock input of the spi, the shifter output is routed to miso, and the shifter input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins.
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 225 figure 15-3. spi module block diagram 15.1.3 spi baud rate generation as shown in figure 15-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr tx buffer (write spid) rx buffer (read spid)
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 226 freescale semiconductor figure 15-4. spi baud rate generation 15.2 external signal description the spi optionally shares four port pins. the function of these pins depends on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins revert to being general-purpose port i/o pins that are not controlled by the spi. 15.2.1 spsck ?spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. when the spi is enabled as a master, this pin is the serial clock output. 15.2.2 mosi ?master data out, slave data in when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data i/o pin (momi). also, the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 15.2.3 miso ?master data in, slave data out when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and master mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 15.2.4 ss ?slave select when the spi is enabled as a slave, this pin is the low-true slave select input. when the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not used by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modfen = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 227 15.3 modes of operation 15.3.1 spi in stop modes the spi is disabled in all stop modes, regardless of the settings before executing the stop instruction. during either stop1 or stop2 mode, the spi module will be fully powered down. upon wake-up from stop1 or stop2 mode, the spi module will be in the reset state. during stop3 mode, clocks to the spi module are halted. no registers are affected. if stop3 is exited with a reset, the spi will be put into its reset state. if stop3 is exited with an interrupt, the spi continues from the state it was in when stop3 was entered. 15.4 register de?ition the spi has ve 8-bit registers to select spi options, control baud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to registers and control bits only by their names, and a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 15.4.1 spi control register 1 (spic1) this read/write register includes the spi enable control, interrupt enables, and con?uration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 00000100 figure 15-5. spi control register 1 (spic1) table 15-1. spic1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ?this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable disabling the spi halts any transfer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ?this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 228 freescale semiconductor note ensure that the spi should not be disabled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur. 15.4.2 spi control register 2 (spic2) this read/write register is used to control optional features of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. 4 mstr master/slave mode select 0 spi module con?ured as a slave spi device 1 spi module con?ured as a master spi device 3 cpol clock polarity this bit effectively places an inverter in series with the clock signal from a master spi or to a slave spi device. refer to section 15.5.1, ?pi clock formats for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ?this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 15.5.1, ?pi clock formats for more details. 0 first edge on spsck occurs at the middle of the ?st cycle of an 8-cycle data transfer 1 first edge on spsck occurs at the start of the ?st cycle of an 8-cycle data transfer 1 ssoe slave select output enable ?this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) control bit to determine the function of the ss pin as shown in table 15-2 . 0 lsbfe lsb first (shifter direction) 0 spi serial data transfers start with most signi?ant bit 1 spi serial data transfers start with least signi?ant bit table 15-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10 ss input for mode fault slave select input 1 1 automatic ss output slave select input 76543210 r000 modfen bidiroe 0 spiswai spc0 w reset 00000000 = unimplemented or reserved figure 15-6. spi control register 2 (spic2) table 15-1. spic1 field descriptions (continued) field description
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 229 15.4.3 spi baud rate register (spibr) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 15-3. spic2 register field descriptions field description 4 modfen master mode-fault function enable when the spi is con?ured for slave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in master mode, this bit determines how the ss pin is used (refer to table 15-2 for more details). 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ?when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is con?ured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data transfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 0 spi uses separate pins for data input and data output 1 spi con?ured for single-wire bidirectional operation 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 00000000 = unimplemented or reserved figure 15-7. spi baud rate register (spibr) table 15-4. spibr register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor this 3-bit ?ld selects one of eight divisors for the spi baud rate prescaler as shown in table 15-5 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 15-4 ). 2:0 spr[2:0] spi baud rate divisor this 3-bit ?ld selects one of eight divisors for the spi baud rate divider as shown in table 15-6 . the input to this divider comes from the spi baud rate prescaler (see figure 15-4 ). the output of this divider is the spi bit rate clock for master mode.
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 230 freescale semiconductor 15.4.4 spi status register (spis) this register has three read-only status bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0. writes have no meaning or effect. table 15-5. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 15-6. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf 0 sptef modf 0000 w reset 00100000 = unimplemented or reserved figure 15-8. spi status register (spis)
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 231 15.4.5 spi data register (spid) reads of this register return the data read from the receive data buffer. writes to this register write data to the transmit data buffer. when the spi is con?ured as a master, writing data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buffer unless the spi transmit buffer empty ?g (sptef) is set, indicating there is room in the transmit buffer to queue a new transmit byte. data may be read from spid any time after sprf is set and before another transfer is ?ished. failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. table 15-7. spis register field descriptions field description 7 sprf spi read buffer full flag sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spid). sprf is cleared by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer 1 data available in the receive data buffer 5 sptef spi transmit buffer empty flag this bit is set when there is room in the transmit data buffer. it is cleared by reading spis with sptef set, followed by writing a data value to the transmit buffer at spid. spis must be read with sptef = 1 before writing data to spid or the spid write will be ignored. sptef generates an sptef cpu interrupt request if the sptie bit in the spic1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. for an idle spi (no data in the transmit buffer or the shift register and no transfer in progress), data written to spid is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. after completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef will be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ?modf is set if the spi is con?ured as a master and the slave select input goes low, indicating some other spi device is also con?ured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spic1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 15-9. spi data register (spid)
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 232 freescale semiconductor 15.5 functional description an spi transfer is initiated by checking for the spi transmit buffer empty ?g (sptef = 1) and then writing a byte of data to the spi data register (spid) in the master spi device. when the spi shift register is available, this byte of data is moved from the transmit data buffer to the shifter, sptef is set to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on the miso pin at one spsck edge and shifted, changing the bit value on the mosi pin, one-half spsck cycle later. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the masters shift register. at the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and sprf is set to indicate the data can be read by reading spid. if another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, sptef is set, and a new transfer is started. normally, spi data is transferred most signi?ant bit (msb) ?st. if the least signi?ant bit ?st enable (lsbfe) bit is set, spi data is shifted lsb ?st. when the spi is con?ured as a slave, its ss pin must be driven low before a transfer starts and ss must stay low throughout the transfer. if a clock format where cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see section 15.5.1, ?pi clock formats ?for more details. because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. the sptef ?g indicates when the transmit buffer has room for a new character. the sprf ?g indicates when a received character is available in the receive data buffer. the received character must be read out of the receive buffer (read spid) before the next transfer is ?ished or a receive overrun error results. in the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 15.5.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from different manufacturers, the spi system has a clock polarity (cpol) bit and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol selectively inserts an inverter in series with the clock. cpha chooses between two different clock phase relationships between the clock and data. figure 15-10 shows the clock formats when cpha = 1. at the top of the ?ure, the eight bit times are shown for reference with bit 1 starting at the ?st spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb ?st and lsb ?st lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a speci? transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 233 pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 15-10. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not de?ed until the ?st spsck edge. the ?st spsck edge shifts the ?st bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slaves ss input is not required to go to its inactive high level between transfers. figure 15-11 shows the clock formats when cpha = 0. at the top of the ?ure, the eight bit times are shown for reference with bit 1 starting as the slave is selected ( ss in goes low), and bit 8 ends at the last spsck edge. the msb ?st and lsb ?st lines show the order of spi data bits depending on the setting bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 234 freescale semiconductor in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a speci? transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the ?st bit time of the transfer and goes back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 15-11. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the ?st data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the ?st spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slaves ss input must go to its inactive high level between transfers. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 235 15.5.2 spi interrupts there are three ?g bits, two interrupt mask bits, and one interrupt vector associated with the spi system. the spi interrupt enable mask (spie) enables interrupts from the spi receiver full ?g (sprf) and mode fault ?g (modf). the spi transmit interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty ?g (sptef). when one of the ?g bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated ?g bits instead of using interrupts. the spi interrupt service routine (isr) should check the ?g bits to determine what event caused the interrupt. the service routine should also clear the ?g bit(s) before returning from the isr (usually near the beginning of the isr). 15.5.3 mode fault detection a mode fault occurs and the mode fault ?g (modf) becomes set when a master spi device detects an error on the ss pin (provided the ss pin is con?ured as the mode fault input signal). the ss pin is con?ured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection feature can be used in a system where more than one spi device might become a master at the same time. the error is detected when a masters ss pin is low, indicating that some other spi device is trying to address this master as if it were a slave. this could indicate a harmful output driver con?ct, so the mode fault logic is designed to disable all spi output drivers when such an error is detected. when a mode fault is detected, modf is set and mstr is cleared to change the spi con?uration back to slave mode. the output drivers on the spsck, mosi, and miso (if not bidirectional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spic1). user software should verify the error condition has been corrected before changing the spi back to master mode.
chapter 15 serial peripheral interface (s08spiv3) mc9s08sh8 mcu series data sheet, rev. 1 236 freescale semiconductor
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 237 chapter 16 timer pulse-width modulator (s08tpmv3) 16.1 introduction the tpm uses one input/output (i/o) pin per channel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?). the tpm shares its i/o pins with general-purpose i/o port pins (refer to the pins and connections chapter for more information). all mc9s08sh8 mcus have two tpm modules. the number of channels available depends on the pin quantity of the package, as shown in table 16-1 : figure 16-1 shows the mc9s08sh8 block diagram with the tpm modules highlighted. 16.1.1 acmp/tpm con?uration information the acmp module can be con?ured to connect the ouput of the analog comparator to tpm1 input capture channel 0 by setting acic in sopt2. with acic set, the tpm1ch0 pin is not available externally regardless of the con?uration of the tpm1 module for channel 0. 16.1.2 tpm con?uration information the external clock for the tpm modules, tpmclk, is selected by setting clks[b:a] = 1:1 in tpmxsc, which selects the tclk pin input. the tclk input on pta0 can be enabled as external clock inputs to both tpm modules and mtim simultaneously. table 16-1. mc9s08sh8 features by mcu and package feature mc9s08sh8/4 pin quantity 20 16 8 tpm1 channels 2 2 1 1 1 the 8-pin device does not have tpm1 or tpm2 channel 1 bonded out, but those timer channels are available to the user to use as software compares. tpm2 channels 2 2 1 1
chapter 16 timer pulse-width modulator (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 238 freescale semiconductor figure 16-1. mc9s08sh8 block diagram highlighting the tpm modules ptb7/scl/extal port b ptb6/sda/xtal ptb5/tpm1ch1/ ss ptb4/tpm2ch1/miso ptb3/pib3/mosi/adp7 ptb2/pib2/spsck/adp6 port a pta1/pia1/tpm2ch0/adp1/acmp ptb1/pib1/txd/adp5 ptb0/pib0/rxd/adp4 port c ptc3/adp11 ptc2/adp10 ptc1/tpm1ch1/adp9 ptc0/tpm1ch0/adp8 pta3/pai3/scl/adp3 pta2/pai2/sda/adp2 pta0/pia0/tpm1ch0/adp0/acmp+ pin can be enabled as part of the ganged output drive feature pta4/acmpo/bkgd/ms pta5/irq/tclk/ reset note 1: port b not available on 8-pin packages see note 1 see note 1, 2 note 2: port c not available on 8-pin or 16-pin packages iic module (iic) serial peripheral interface module (spi) user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lvd interface module (sci) serial communications 8-bit modulo timer module (mtim) voltage regulator debug module (dbg) miso scl sda mosi spsck rxd txd low-power oscillator 40-mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xosc) extal xtal v ss v dd v ssa v dda v refl v refh analog-to-digital converter (adc) 10-bit ss tclk bkgd/ms 16-bit timer/pwm module (tpm2) tclk real-time counter (rtc) (mc9s08sh8 = 8,192 bytes) (MC9S08SH4 = 4096 bytes) (mc9s08sh8 = 512 bytes) analog comparator (acmp) acmpo acmp acmp+ tpm2ch0 tpm2ch1 adp11-adp0 16-bit timer/pwm module (tpm1) tclk tpm1ch0 tpm1ch1 irq irq (MC9S08SH4 = 256 bytes) note 3: v dda /v refh and v ssa /v refl , are double bonded to v dd and v ss respectively. notes = see note 3
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 239 16.1.3 features the tpm includes these distinctive features: one to eight channels: each channel may be input capture, output compare, or edge-aligned pwm rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action selectable polarity on pwm outputs module may be con?ured for buffered, center-aligned pulse-width-modulation (cpwm) on all channels timer clock source selectable as prescaled bus clock, ?ed system clock, or an external clock pin prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit external clock pin may be shared with any timer channel pin or a separated input pin 16-bit free-running or modulo up/down count operation timer system enable one interrupt per channel plus terminal count interrupt 16.1.4 modes of operation in general, tpm channels may be independently con?ured to operate in input capture, output compare, or edge-aligned pwm modes. a control bit allows the whole tpm (all channels) to switch to center-aligned pwm mode. when center-aligned pwm mode is selected, input capture, output compare, and edge-aligned pwm functions are not available on any channels of this tpm module. when the microcontroller is in active bdm background or bdm foreground mode, the tpm temporarily suspends all counting until the microcontroller returns to normal user operating mode. during stop mode, all system clocks, including the main oscillator, are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. provided the tpm does not need to produce a real time reference or provide the interrupt source(s) needed to wake the mcu from wait mode, the user can save power by disabling tpm functions before entering wait mode. input capture mode when a selected edge event occurs on the associated mcu pin, the current value of the 16-bit timer counter is captured into the channel value register and an interrupt ?g bit is set. rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. output compare mode when the value in the timer counter register matches the channel value register, an interrupt ?g bit is set, and a selected output action is forced on the associated mcu pin. the output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 240 freescale semiconductor edge-aligned pwm mode the value of a 16-bit modulo register plus 1 sets the period of the pwm output signal. the channel value register sets the duty cycle of the pwm output signal. the user may also choose the polarity of the pwm output signal. interrupts are available at the end of the period and at the duty-cycle transition point. this type of pwm signal is called edge-aligned because the leading edges of all pwm signals are aligned with the beginning of the period, which is the same for all channels within a tpm. center-aligned pwm mode twice the value of a 16-bit modulo register sets the period of the pwm output, and the channel-value register sets the half-duty-cycle duration. the timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. as the count matches the channel value register while counting down, the pwm output becomes active. when the count matches the channel value register while counting up, the pwm output becomes inactive. this type of pwm signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. this type of pwm is required for types of motors used in small appliances. this is a high-level description only. detailed descriptions of operating modes are in later sections. 16.1.5 block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn (timer channel n) where n is the channel number (1-8). the tpm shares its i/o pins with general purpose i/o port pins (refer to i/o pin descriptions in full-chip speci?ation for the speci? chip implementation). figure 16-2 shows the tpm structure. the central component of the tpm is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. the tpm counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned pwm functions. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter (the values 0x0000 or 0xffff effectively make the counter free running). software can read the counter value at any time without affecting the counting sequence. any write to either half of the tpmxcnt counter resets the counter, regardless of the data value written.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 241 figure 16-2. tpm block diagram prescale and select 16-bit comparator ps2:ps1:ps0 tof toie inter- 16-bit counter rupt logic 16-bit comparator 16-bit latch els0b els0a port channel 0 ch0ie ch0f logic inter- rupt logic cpwms ms0b ms0a counter reset clksb:clksa 1, 2, 4, 8, 16, 32, 64, bus clock fixed system clock external clock sync 16-bit comparator 16-bit latch channel 1 els1b els1a ch1ie ch1f internal bus port logic inter- rupt logic ms1b ms1a 16-bit comparator 16-bit latch channel 7 els7b els7a ch7ie ch7f port logic inter- rupt logic ms7b ms7a up to 8 channels clock source select off, bus, fixed system clock, ext or 128 tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxch0 tpmxch1 tpmxc7vh:tpmxc7vl tpmxch7
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 242 freescale semiconductor the tpm channels are programmable independently as input capture, output compare, or edge-aligned pwm channels. alternately, the tpm can be con?ured to produce cpwm outputs on all channels. when the tpm is con?ured for cpwms, the counter operates as an up/down counter; input capture, output compare, and epwm functions are not practical. if a channel is con?ured as input capture, an internal pullup device may be enabled for that channel. the details of how a module interacts with pin controls depends upon the chip implementation because the i/o pins and associated general purpose i/o controls are not part of the module. refer to the discussion of the i/o port logic in a full-chip speci?ation. because center-aligned pwms are usually used to drive 3-phase ac-induction motors and brushless dc motors, they are typically used in sets of three or six channels. 16.2 signal description table 16-2 shows the user-accessible signals for the tpm. the number of channels may be varied from one to eight. when an external clock is included, it can be shared with the same pin as any tpm channel; however, it could be connected to a separate input pin. refer to the i/o pin descriptions in full-chip speci?ation for the speci? chip implementation. refer to documentation for the full-chip for details about reset states, port connections, and whether there is any pullup device on these pins. tpm channel pins can be associated with general purpose i/o pins and have passive pullup devices which can be enabled with a control bit when the tpm or general purpose i/o controls have con?ured the associated pin as an input. when no tpm function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose i/o controls, including the port-data and data-direction registers. immediately after reset, no tpm functions are enabled, so all associated pins revert to general purpose i/o control. 16.2.1 detailed signal descriptions this section describes each user-accessible pin signal in detail. although table 16-2 grouped all channel pins together, any tpm pin can be shared with the external clock source signal. since i/o pin logic is not part of the tpm, refer to full-chip documentation for a speci? derivative for more details about the interaction of tpm pin functions and general purpose i/o controls including port data, data direction, and pullup controls. table 16-2. signal properties name function extclk 1 1 when preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. external clock source which may be selected to drive the tpm counter. tpmxchn 2 2 n=channel number (1 to 8) i/o pin associated with tpm channel n
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 243 16.2.1.1 extclk ?external clock source control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the tpm prescaler and subsequently the 16-bit tpm counter. the external clock source is synchronized in the tpm. the bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the frequency of the bus-rate clock, to meet nyquist criteria and allowing for jitter. the external clock signal shares the same pin as a channel i/o pin, so the channel pin will not be usable for channel i/o function when selected as the external clock source. it is the users responsibility to avoid such settings. if this pin is used as an external clock source (clksb:clksa = 1:1), the channel can still be used in output compare mode as a software timer (elsnb:elsna = 0:0). 16.2.1.2 tpmxchn ?tpm channel n i/o pin(s) each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the channel con?uration. the tpm pins share with general purpose i/o pins, where each pin has a port data register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. the tpm channel does not control the i/o pin when (elsnb:elsna = 0:0) or when (clksb:clksa = 0:0) so it normally reverts to general purpose i/o control. when cpwms = 1 (and elsnb:elsna not = 0:0), all channels within the tpm are con?ured for center-aligned pwm and the tpmxchn pins are all controlled by the tpm system. when cpwms=0, the msnb:msna control bits determine whether the channel is con?ured for input capture, output compare, or edge-aligned pwm. when a channel is con?ured for input capture (cpwms=0, msnb:msna = 0:0 and elsnb:elsna not = 0:0), the tpmxchn pin is forced to act as an edge-sensitive input to the tpm. elsnb:elsna control bits determine what polarity edge or edges will trigger input-capture events. a synchronizer based on the bus clock is used to synchronize input edges to the bus clock. this implies the minimum pulse width?hat can be reliably detected?n an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). tpm uses this pin as an input capture input to override the port data and data direction controls for the same pin. when a channel is con?ured for output compare (cpwms=0, msnb:msna = 0:1 and elsnb:elsna not = 0:0), the associated data direction control is overridden, the tpmxchn pin is considered an output controlled by the tpm, and the elsnb:elsna control bits determine how the pin is controlled. the remaining three combinations of elsnb:elsna determine whether the tpmxchn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. when the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event?hen the pin is toggled.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 244 freescale semiconductor when a channel is con?ured for edge-aligned pwm (cpwms=0, msnb=1 and elsnb:elsna not = 0:0), the data direction is overridden, the tpmxchn pin is forced to be an output controlled by the tpm, and elsna controls the polarity of the pwm output signal on the pin. when elsnb:elsna=1:0, the tpmxchn pin is forced high at the start of each new period (tpmxcnt=0x0000), and the pin is forced low when the channel value register matches the timer counter. when elsna=1, the tpmxchn pin is forced low at the start of each new period (tpmxcnt=0x0000), and the pin is forced high when the channel value register matches the timer counter. figure 16-3. high-true pulse of an edge-aligned pwm figure 16-4. low-true pulse of an edge-aligned pwm chnf bit tof bit 0... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit 0... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 245 when the tpm is con?ured for center-aligned pwm (and elsnb:elsna not = 0:0), the data direction for all channels in this tpm are overridden, the tpmxchn pins are forced to be outputs controlled by the tpm, and the elsna bits control the polarity of each tpmxchn output. if elsnb:elsna=1:0, the corresponding tpmxchn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the tpmxchn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. if elsna=1, the corresponding tpmxchn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the tpmxchn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter. figure 16-5. high-true pulse of a center-aligned pwm figure 16-6. low-true pulse of a center-aligned pwm chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 t pmxcnth:tpmxcntl tpmxchn chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 t pmxcnth:tpmxcntl tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 246 freescale semiconductor 16.3 register de?ition this section consists of register descriptions in address order. a typical mcu system may contain multiple tpms, and each tpm may have one to eight channels, so register names include placeholder characters to identify which tpm and which channel is being referenced. for example, tpmxcnsc refers to timer (tpm) x, channel n. tpm1c2sc would be the status and control register for channel 2 of timer 1. 16.3.1 tpm status and control register (tpmxsc) tpmxsc contains the over?w status ?g and control bits used to con?ure the interrupt enable, tpm con?uration, clock source, and prescale factor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w0 reset 00000000 figure 16-7. tpm status and control register (tpmxsc) table 16-3. tpmxsc field descriptions field description 7 tof timer over?w ?g. this read/write ?g is set when the tpm counter resets to 0x0000 after reaching the modulo value programmed in the tpm counter modulo registers. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm over?w occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. this is done so a tof interrupt request cannot be lost during the clearing sequence for a previous tof. reset clears tof. writing a logic 1 to tof has no effect. 0 tpm counter has not reached modulo value or over?w 1 tpm counter has over?wed 6 toie timer over?w interrupt enable. this read/write bit enables tpm over?w interrupts. if toie is set, an interrupt is generated when tof equals one. reset clears toie. 0 tof interrupts inhibited (use for software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select. when present, this read/write bit selects cpwm operating mode. by default, the tpm operates in up-counting mode for input capture, output compare, and edge-aligned pwm functions. setting cpwms recon?ures the tpm to operate in up/down counting mode for cpwm functions. reset clears cpwms. 0 all channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channels status and control register. 1 all channels operate in center-aligned pwm mode.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 247 16.3.2 tpm-counter registers (tpmxcnth:tpmxcntl) the two read-only tpm counter registers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other half is read. this allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. the coherency mechanism is automatically restarted by an mcu reset or any write to the timer status/control register (tpmxsc). 4? clks[b:a] clock source selects. as shown in table 16-4 , this 2-bit ?ld is used to disable the tpm system or select one of three clock sources to drive the counter prescaler. the ?ed system clock source is only meaningful in systems with a pll-based system clock. when there is no pll, the ?ed-system clock source is the same as the bus rate clock. the external source is synchronized to the bus clock by tpm module, and the ?ed system clock source (when a pll is present) is synchronized to the bus clock by an on-chip synchronization circuit. when a pll is present but not enabled, the ?ed-system clock source is the same as the bus-rate clock. 2? ps[2:0] prescale factor select. this 3-bit ?ld selects one of 8 division factors for the tpm clock input as shown in table 16-5 . this prescaler is located after any clock source synchronization or clock source selection so it affects the clock source selected to drive the tpm system. the new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. table 16-4. tpm-clock-source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (tpm counter disable) 01 bus rate clock 10 fixed system clock 11 external source table 16-5. prescale factor selection ps2:ps1:ps0 tpm clock source divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 table 16-3. tpmxsc field descriptions (continued) field description
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 248 freescale semiconductor reset clears the tpm counter registers. writing any value to tpmxcnth or tpmxcntl also clears the tpm counter (tpmxcnth:tpmxcntl) and resets the coherency mechanism, regardless of the data involved in the write. when bdm is active, the timer counter is frozen (this is the value that will be read by user); the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active, even if one or both counter halves are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. in bdm mode, writing any value to tpmxsc, tpmxcnth or tpmxcntl registers resets the read coherency mechanism of the tpmxcnth:l registers, regardless of the data involved in the write. 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock, and the over?w ?g (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits the tof bit and over?w interrupts until the other byte is written. reset sets the tpm counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). writing to either byte (tpmxmodh or tpmxmodl) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), then the registers are updated when the second byte is written if (clksb:clksa not = 0:0), then the registers are updated after both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff the latching mechanism may be manually reset by writing to the tpmxsc address (whether bdm is active or not). 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter reset 00000000 figure 16-8. tpm counter register high (tpmxcnth) 76543210 r bit 7 654321 bit 0 w any write to tpmxcntl clears the 16-bit counter reset 00000000 figure 16-9. tpm counter register low (tpmxcntl)
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 249 when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxsc register) such that the buffer latches remain in the state they were in when the bdm became active, even if one or both halves of the modulo register are written while bdm is active. any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while bdm is active. reset the tpm counter before writing to the tpm modulo registers to avoid confusion about when the ?st counter over?w will occur. 16.3.4 tpm channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel-interrupt-status ?g and control bits used to con?ure the interrupt enable, channel con?uration, and pin function. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 16-10. tpm counter modulo register high (tpmxmodh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 16-11. tpm counter modulo register low (tpmxmodl) 76543210 r chnf chnie msnb msna elsnb elsna 00 w0 reset 00000000 = unimplemented or reserved figure 16-12. tpm channel n status and control register (tpmxcnsc)
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 250 freescale semiconductor table 16-6. tpmxcnsc field descriptions field description 7 chnf channel n ?g. when channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned/center-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. when channel n is an edge-aligned/center-aligned pwm channel and the duty cycle is set to 0% or 100%, chnf will not be set even when the value in the tpm counter registers matches the value in the tpm channel n value registers. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf remains set after the clear sequence completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost due to clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event on channel n 6 chnie channel n interrupt enable. this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use for software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n. when cpwms=0, msnb=1 con?ures tpm channel n for edge-aligned pwm mode. refer to the summary of channel mode and setup controls in table 16-7 . 4 msna mode select a for tpm channel n. when cpwms=0 and msnb=0, msna con?ures tpm channel n for input-capture mode or output compare mode. refer to table 16-7 for a summary of channel mode and setup controls. note: if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3? elsnb elsna edge/level select bits. depending upon the operating mode for the timer channel as set by cpwms:msnb:msna and shown in table 16-7 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 con?ures the related timer pin as a general purpose i/o pin not related to any timer functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. table 16-7. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode con?uration x xx 00 pin not used for tpm - revert to general purpose i/o or other peripheral control
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 251 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) these read/write registers contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the channel registers are cleared by reset. in input capture mode, reading either byte (tpmxcnvh or tpmxcnvl) latches the contents of both bytes into a buffer where they remain latched until the other half is read. this latching mechanism also resets 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 01 output compare toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 16-13. tpm channel value register high (tpmxcnvh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 16-14. tpm channel value register low (tpmxcnvl) table 16-7. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode con?uration
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 252 freescale semiconductor (becomes unlatched) when the tpmxcnsc register is written (whether bdm mode is active or not). any write to the channel registers will be ignored during the input capture mode. when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxcnsc register) such that the buffer latches remain in the state they were in when the bdm became active, even if one or both halves of the channel register are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. the value read from the tpmxcnvh and tpmxcnvl registers in bdm mode is the value of these registers and not the value of their read buffer. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. after both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of clksb:clksa bits and the selected mode, so: if (clksb:clksa = 0:0), then the registers are updated when the second byte is written. if (clksb:clksa not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the tpm counter (end of the prescaler counting). if (clksb:clksa not = 0:0 and in epwm or cpwm modes), then the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. the latching mechanism may be manually reset by writing to the tpmxcnsc register (whether bdm mode is active or not). this latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. when bdm is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active even if one or both halves of the channel register are written while bdm is active. any write to the channel registers bypasses the buffer latches and directly write to the channel register while bdm is active. the values written to the channel register while bdm is active are used for pwm & output compare operation once normal execution resumes. writes to the channel registers while bdm is active do not interfere with partial completion of a coherency sequence. after the coherency mechanism has been fully exercised, the channel registers are updated using the buffered values written (while bdm was not active) by the user. 16.4 functional description all tpm functions are associated with a central 16-bit counter which allows ?xible selection of the clock source and prescale factor. there is also a 16-bit modulo register associated with the main counter. the cpwms control bit chooses between center-aligned pwm operation for all channels in the tpm (cpwms=1) or general purpose timing functions (cpwms=0) where each channel can independently be con?ured to operate in input capture, output compare, or edge-aligned pwm mode. the cpwms control bit is located in the main tpm status and control register because it affects all channels within the tpm and in?ences the way the main counter operates. (in cpwm mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.)
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 253 the following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, end-of-count over?w, up-counting vs. up/down counting, and manual counter reset. 16.4.1.1 counter clock source the 2-bit ?ld, clksb:clksa, in the timer status and control register (tpmxsc) selects one of three possible clock sources or off (which effectively disables the tpm). see table 16-4 . after any mcu reset, clksb:clksa=0:0 so no clock source is selected, and the tpm is in a very low power state. these control bits may be read or written at any time and disabling the timer (writing 00 to the clksb:clksa ?ld) does not affect the values in the counter or other timer registers.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 254 freescale semiconductor the bus rate clock is the main system bus clock for the mcu. this clock source requires no synchronization because it is the clock that is used for all internal mcu activities including operation of the cpu and buses. in mcus that have no pll or the pll is not engaged, the ?ed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. when a pll is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the timer counter so counter transitions will be properly aligned to bus-clock transitions. a synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. the external clock source may be connected to any tpm channel pin. this clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. the bus-rate clock drives the synchronizer; therefore, to meet nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by four. with ideal clocks the external clock can be as fast as bus clock divided by four. when the external clock source shares the tpm channel pin, this pin should not be used for other channel timing functions. for example, it would be ambiguous to con?ure channel 0 for input capture when the tpm channel 0 pin was also being used as the timer external clock source. (it is the users responsibility to avoid such settings.) the tpm channel could still be used in output compare mode for software timing functions (pin controls set not to affect the tpm channel pin). 16.4.1.2 counter over?w and modulo reset an interrupt ?g and enable are associated with the 16-bit main counter. the ?g (tof) is a software-accessible indication that the timer counter has over?wed. the enable signal selects between software polling (toie=0) where no hardware interrupt is generated, or interrupt-driven operation (toie=1) where a static hardware interrupt is generated whenever the tof ?g is equal to one. the conditions causing tof to become set depend on whether the tpm is con?ured for center-aligned pwm (cpwms=1). in the simplest mode, there is no modulus limit and the tpm is not in cpwms=1 mode. in this case, the 16-bit timer counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the tpm is in center-aligned pwm mode (cpwms=1), the tof ?g gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). this corresponds to the end of a pwm period (the 0x0000 count value corresponds to the center of a period). table 16-8. tpm clock source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (tpm counter disabled) 01 bus rate clock 10 fixed system clock 11 external source
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 255 16.4.1.3 counting modes the main timer counter has two counting modes. when center-aligned pwm is selected (cpwms=1), the counter operates in up/down counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is speci?d, the counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up counting. both 0x0000 and the terminal count value are normal length counts (one timer clock period long). in this mode, the timer over?w ?g (tof) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 16.4.1.4 manual counter reset the main timer counter can be manually reset at any time by writing any value to either half of tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only half of the counter was read before resetting the count. 16.4.2 channel mode selection provided cpwms=0, the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and edge-aligned pwm. 16.4.2.1 input capture mode with the input-capture function, the tpm can capture the time at which an external event occurs. when an active edge occurs on the pin of an input-capture channel, the tpm latches the contents of the tpm counter into the channel-value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. in input capture mode, the tpmxcnvh and tpmxcnvl registers are read only. when either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an input capture event sets a ?g bit (chnf) which may optionally generate a cpu interrupt request. while in bdm, the input capture function works as con?ured by the user. when an external event occurs, the tpm latches the contents of the tpm counter (which is frozen because of the bdm mode) into the channel value registers and sets the ?g bit. 16.4.2.2 output compare mode with the output-compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reaches the value in the channel-value registers of an output-compare channel, the tpm can set, clear, or toggle the channel pin.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 256 freescale semiconductor in output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated at the next change of the tpm counter (end of the prescaler counting) after the second byte is written. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an output compare event sets a ?g bit (chnf) which may optionally generate a cpu-interrupt request. 16.4.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer counter (cpwms=0) and can be used when other channels in the same tpm are con?ured for input capture or output compare functions. the period of this pwm signal is determined by the value of the modulus register (tpmxmodh:tpmxmodl) plus 1. the duty cycle is determined by the setting in the timer channel register (tpmxcnvh:tpmxcnvl). the polarity of this pwm signal is determined by the setting in the elsna control bit. 0% and 100% duty cycle cases are possible. the output compare value in the tpm channel registers determines the pulse width (duty cycle) of the pwm signal ( figure 16-15 ). the time between the modulus over?w and the output compare is the pulse width. if elsna=0, the counter over?w forces the pwm signal high, and the output compare forces the pwm signal low. if elsna=1, the counter over?w forces the pwm signal low, and the output compare forces the pwm signal high. figure 16-15. pwm period and pulse width (elsna=0) when the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting. this implies that the modulus setting must be less than 0xffff in order to get 100% duty cycle. because the tpm may be used in an 8-bit mcu, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxcnvh and tpmxcnvl, actually write to buffer registers. in edge-aligned pwm mode, values are transferred to the corresponding timer-channel registers according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 257 the tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. 16.4.2.4 center-aligned pwm mode this type of pwm output uses the up/down counting mode of the timer counter (cpwms=1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal while the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) period = 2 x (tpmxmodh:tpmxmodl); tpmxmodh:tpmxmodl=0x0001-0x7fff if the channel-value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if you do not need to generate 100% duty cycle). this is not a signi?ant limitation. the resulting period would be much longer than required for normal applications. tpmxmodh:tpmxmodl=0x0000 is a special case that should not be used with center-aligned pwm mode. when cpwms=0, this case corresponds to the counter running free from 0x0000 through 0xffff, but when cpwms=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. the output compare value in the tpm channel registers (times 2) determines the pulse width (duty cycle) of the cpwm signal ( figure 16-16). if elsna=0, a compare occurred while counting up forces the cpwm output signal low and a compare occurred while counting down forces the output high. the counter counts up until it reaches the modulo setting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 16-16. cpwm period and pulse width (elsna=0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also required for some types of motor drives. period pulse width count= count= 0 count= output compare (count down) output compare (count up) tpmxchn 2 x tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl tpmxmodh:tpmxmodl tpmxmodh:tpmxmodl
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 258 freescale semiconductor input capture, output compare, and edge-aligned pwm functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a tpm must be used in cpwm mode when cpwms=1. the tpm may be used in an 8-bit mcu. the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, actually write to buffer registers. in center-aligned pwm mode, the tpmxcnvh:l registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff. when tpmxcnth:tpmxcntl=tpmxmodh:tpmxmodl, the tpm can optionally generate a tof interrupt (at the end of this count). writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo registers. writing to tpmxcnsc cancels any values written to the channel value registers and resets the coherency mechanism for tpmxcnvh:tpmxcnvl. 16.5 reset overview 16.5.1 general the tpm is reset whenever any mcu reset occurs. 16.5.2 description of reset operation reset clears the tpmxsc register which disables clocks to the tpm and disables timer over?w interrupts (toie=0). cpwms, msnb, msna, elsnb, and elsna are all cleared which con?ures all tpm channels for input-capture operation with the associated pins disconnected from i/o pin logic (so all mcu pins related to the tpm revert to general purpose i/o pins). 16.6 interrupts 16.6.1 general the tpm generates an optional interrupt for the main counter over?w and an interrupt for each channel. the meaning of channel interrupts depends on each channels mode of operation. if the channel is con?ured for input capture, the interrupt ?g is set each time the selected input capture edge is recognized. if the channel is con?ured for output compare or pwm modes, the interrupt ?g is set each time the main timer counter matches the value in the 16-bit channel value register.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 259 all tpm interrupts are listed in table 16-9 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the tpm and getting recognized by the separate interrupt processing logic. the tpm module will provide a high-true interrupt signal. vectors and priorities are determined at chip integration time in the interrupt module so refer to the users guide for the interrupt module or to the chips complete documentation for details. 16.6.2 description of interrupt operation for each interrupt source in the tpm, a ?g bit is set upon recognition of the interrupt condition such as timer over?w, channel-input capture, or output-compare events. this ?g may be read (polled) by software to determine that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt ?g equals one. the users software must perform a sequence of steps to clear the interrupt ?g before returning from the interrupt-service routine. tpm interrupt ?gs are cleared by a two-step process including a read of the ?g bit while it is set (1) followed by a write of zero (0) to the bit. if a new event is detected between these two steps, the sequence is reset and the interrupt ?g remains set after the second step to avoid the possibility of missing the new event. 16.6.2.1 timer over?w interrupt (tof) description the meaning and details of operation for tof interrupts varies slightly depending upon the mode of operation of the tpm system (general purpose timing functions versus center-aligned pwm operation). the ?g is cleared by the two step sequence described above. 16.6.2.1.1 normal case normally tof is set when the timer counter changes from 0xffff to 0x0000. when the tpm is not con?ured for center-aligned pwm (cpwms=0), tof gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. this case corresponds to the normal meaning of counter over?w. table 16-9. interrupt summary interrupt local enable source description tof toie counter over?w set each time the timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) chnf chnie channel event an input capture or output compare event took place on channel n
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 260 freescale semiconductor 16.6.2.1.2 center-aligned pwm case when cpwms=1, tof gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). in this case the tof corresponds to the end of a pwm period. 16.6.2.2 channel event interrupt description the meaning of channel interrupts depends on the channels current mode (input-capture, output-compare, edge-aligned pwm, or center-aligned pwm). 16.6.2.2.1 input capture events when a channel is con?ured as an input capture channel, the elsnb:elsna control bits select no edge (off), rising edges, falling edges or any edge as the edge which triggers an input capture event. when the selected edge is detected, the interrupt ?g is set. the ?g is cleared by the two-step sequence described in section 16.6.2, ?escription of interrupt operation . 16.6.2.2.2 output compare events when a channel is con?ured as an output compare channel, the interrupt ?g is set each time the main timer counter matches the 16-bit value in the channel value register. the ?g is cleared by the two-step sequence described section 16.6.2, ?escription of interrupt operation . 16.6.2.2.3 pwm end-of-duty-cycle events for channels con?ured for pwm operation there are two possibilities. when the channel is con?ured for edge-aligned pwm, the channel ?g gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. when the channel is con?ured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel ?g is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. the ?g is cleared by the two-step sequence described section 16.6.2, ?escription of interrupt operation . 16.7 differences between tpm v2 to tpm v3 1. write to tpmxcnth:l registers ( section 16.3.2, ?pm-counter registers (tpmxcnth:tpmxcntl)) [se110-tpm case 7] any write to tpmxcnth or tpmxcntl registers in tpm v3 clears the tpm counter (tpmxcnth:l) and the prescaler counter. instead, in the tpm v2 only the tpm counter is cleared in this case. 2. read of tpmxcnth:l registers ( section 16.3.2, ?pm-counter registers (tpmxcnth:tpmxcntl)) in tpm v3, any read of tpmxcnth:l registers during bdm mode returns the value of the tpm counter that is frozen. in tpm v2, if only one byte of the tpmxcnth:l registers was read before the bdm mode became active, then any read of tpmxcnth:l registers during
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 261 bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the frozen tpm counter value. this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxsc, tpmxcnth or tpmxcntl. instead, in these conditions the tpm v2 does not clear this read coherency mechanism. 3. read of tpmxcnvh:l registers ( section 16.3.5, ?pm channel value registers (tpmxcnvh:tpmxcnvl)) in tpm v3, any read of tpmxcnvh:l registers during bdm mode returns the value of the tpmxcnvh:l register. in tpm v2, if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, then any read of tpmxcnvh:l registers during bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the value in the tpmxcnvh:l registers. this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxcnsc. instead, in this condition the tpm v2 does not clear this read coherency mechanism. 4. write to tpmxcnvh:l registers input capture mode ( section 16.4.2.1, ?nput capture mode ) in this mode the tpm v3 does not allow the writes to tpmxcnvh:l registers. instead, the tpm v2 allows these writes. output compare mode ( section 16.4.2.2, ?utput compare mode ) in this mode and if (clksb:clksa not = 0:0), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the prescaler counting) after the second byte is written. instead, the tpm v2 always updates these registers when their second byte is written. edge-aligned pwm ( section 16.4.2.3, ?dge-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes were written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to $0000. center-aligned pwm ( section 16.4.2.4, ?enter-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes were written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). 5. center-aligned pwm ( section 16.4.2.4, ?enter-aligned pwm mode ) tpmxcnvh:l = tpmxmodh:l [se110-tpm case 1] in this case, the tpm v3 produces 100% duty cycle. instead, the tpm v2 produces 0% duty cycle.
chapter 16 timer/pwm module (s08tpmv3) mc9s08sh8 mcu series data sheet, rev. 1 262 freescale semiconductor tpmxcnvh:l = (tpmxmodh:l - 1) [se110-tpm case 2] in this case, the tpm v3 produces almost 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. tpmxcnvh:l is changed from 0x0000 to a non-zero value [se110-tpm case 3 and 5] in this case, the tpm v3 waits for the start of a new pwm period to begin using the new duty cycle setting. instead, the tpm v2 changes the channel output at the middle of the current pwm period (when the count reaches 0x0000). tpmxcnvh:l is changed from a non-zero value to 0x0000 [se110-tpm case 4] in this case, the tpm v3 ?ishes the current pwm period using the old duty cycle setting. instead, the tpm v2 ?ishes the current pwm period using the new duty cycle setting. 6. write to tpmxmodh:l registers in bdm mode ( section 16.3.3, ?pm counter modulo registers (tpmxmodh:tpmxmodl) ) in the tpm v3 a write to tpmxsc register in bdm mode clears the write coherency mechanism of tpmxmodh:l registers. instead, in the tpm v2 this coherency mechanism is not cleared when there is a write to tpmxsc register.
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 263 chapter 17 development support 17.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a single-wire debug interface to the target mcu that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoints, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through commands fed into the target mcu via the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 forcing active background the method for forcing active background mode depends on the speci? hcs08 derivative. for the mc9s08sh8, you can force active background after a power-on reset by holding the bkgd pin low as the device exits the reset condition. you can also force active background by driving bkgd low immediately after a serial background command that writes a one to the bdfr bit in the sbdfr register. other causes of reset including an external pin reset or an internally generated error reset ignore the state of the bkgd pin and reset into normal user mode. if no debug pod is connected to the bkgd pin, the mcu will always reset into normal operating mode.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 264 freescale semiconductor 17.1.2 features features of the bdc module include: single pin for mode selection and background communications bdc registers are not located in the memory map sync command to determine target communications rate non-intrusive commands for memory access active background mode commands for cpu register access go and trace1 commands background command can wake cpu from stop or wait modes one hardware address breakpoint built into bdc oscillator runs in stop mode, if bdc enabled cop watchdog disabled while in active background mode features of the ice system include: two trigger comparators: two address + read/write (r/w) or one full address + data + r/w flexible 8-word by 16-bit fifo (?st-in, ?st-out) buffer for capture information: change-of-?w addresses or event-only data two types of breakpoints: tag breakpoints for instruction opcodes force breakpoints for any address access nine trigger modes: basic: a-only, a or b sequence: a then b full: a and b data, a and not b data event (store data): event-only b, a then event-only b range: inside range (a address b), outside range (address < a or address > b) 17.2 background debug controller (bdc) all mcus in the hcs08 family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands allow the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 265 non-intrusive commands can be executed at any time even while the users program is running. non-intrusive commands allow a user to read or write mcu memory locations or access status and control registers within the background debug controller. typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. depending on the development tool vendor, this interface pod may use a standard rs-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (usb) to communicate between the host pc and the pod. the pod typically connects to the target system with ground, the bkgd pin, reset, and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. sometimes v dd can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 17-1. bdm tool connector 17.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communication of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the users application program. this pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. bdc serial communications use a custom serial protocol ?st introduced on the m68hc12 family of microcontrollers. this protocol assumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most signi?ant bit ?st (msb ?st). for a detailed description of the communications protocol, refer to section 17.2.2, ?ommunication details. if a host is attempting to communicate with a target mcu that has an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync response signal from which the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. unlike typical open-drain pins, the external rc time constant on this pin, which is in?enced by external capacitance, plays almost no role in signal rise time. the custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level con?cts. refer to section 17.2.2, ?ommunication details , for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 266 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode. when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci? conditions for forcing active background depend upon the hcs08 derivative (refer to the introduction to this development support section). it is not necessary to reset the target mcu to communicate with it through the background debug interface. 17.2.2 communication details the bdc serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external controller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb ?st at 16 bdc clock cycles per bit (nominal speed). the interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and control register allows the user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or low level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 267 figure 17-2 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. figure 17-2. bdc host-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 268 freescale semiconductor figure 17-3 shows the host receiving a logic 1 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 17-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 269 figure 17-4 shows the host receiving a logic 0 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target hcs08 ?ishes it. because the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 bdc clock cycles, then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 17-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 270 freescale semiconductor 17.2.3 bdc commands bdc commands are sent serially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-?st using a custom bdc communications protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 17-1 shows all hcs08 bdc commands, a shorthand description of their coding structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 17-1 to describe the coding structure of the bdc commands. commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most signi?ant bit ?st) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in the target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target-to-host direction (from bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-target direction (for bdcbkpt breakpoint register)
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 271 table 17-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss read bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd read a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusive c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. report status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 272 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to use for bdc communications until after it has analyzed the response to the sync command. to issue a sync command, the host: drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) removes all drive to the bkgd pin so it reverts to high impedance monitors the bkgd pin for the sync response pulse the target, upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal bdc communications): waits for bkgd to return to a logic high delays 16 cycles to allow the host to stop driving the high speedup pulse drives bkgd low for 128 bdc clock cycles drives a 1-cycle high speedup pulse to force a fast rise time on bkgd removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent bdc communications. typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware breakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this breakpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the ?st instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten) control bit in the bdc status and control register (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is disabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg) includes circuitry for two additional hardware breakpoints that are more ?xible than the simple breakpoint in the bdc module.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 273 17.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a ?xible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status registers that are accessible in the users memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug modules functions are used during development, and user programs rarely access any of the control and status registers for the debug module. the one exception is that the debug system can provide the means to implement a form of rom patching. this topic is discussed in greater detail in section 17.3.6, ?ardware breakpoints . 17.3.1 comparators a and b two 16-bit comparators (a and b) can optionally be quali?d with the r/w signal and an opcode tracking circuit. separate control bits allow you to ignore r/w for each comparator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the speci?d address is actually executed as opposed to only being read from memory into the instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temporarily during all bdc accesses. the a comparator is always associated with the 16-bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpus write data bus is used. otherwise, the cpus read data bus is used. the currently selected trigger mode determines what the debugger logic does when a comparator detects a quali?d match condition. a match can cause: generation of a breakpoint to the cpu storage of data bus values into the fifo starting to store change-of-?w addresses into the fifo (begin type trace) stopping the storage of change-of-?w addresses into the fifo (end type trace) 17.3.2 bus capture information and fifo operation the usual way to use the fifo is to setup the trigger mode and other control options, then arm the debugger. when the fifo has ?led or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo. status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the information is shifted by one position and
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 274 freescale semiconductor the host must perform ((8 cnt) 1) dummy reads of the fifo to advance it to the ?st signi?ant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-?w addresses. in these cases, read dbgfh then dbgfl to get one coherent word of information out of the fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 17.3.5, ?rigger modes ), 8-bit data information is stored into the fifo. in these cases, the high-order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. each time dbgfl is read, the fifo is shifted so the next data value is available through the fifo data port at dbgfl. in trigger modes where the fifo is storing change-of-?w addresses, there is a delay between cpu addresses and the input side of the fifo. because of this delay, if the trigger event itself is a change-of-?w address or a change-of-?w address appears during the next two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-?w, it will be saved as the last change-of-?w entry for that debug run. the fifo can also be used to generate a pro?e of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the address of the most-recently fetched opcode to be saved in the fifo. to use the pro?ing feature, a host debugger would read addresses out of the fifo by reading dbgfh then dbgfl at regular periodic intervals. the ?st eight values would be discarded because they correspond to the eight dbgfl reads needed to initially ?l the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a pro?e of executed instruction addresses. 17.3.3 change-of-flow information to minimize the amount of information stored in the fifo, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. with knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-?w information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). because bra and brn instructions are not conditional, these events do not cause change-of-?w information to be stored in the fifo. indirect jmp and jsr instructions use the current contents of the h:x index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-?w information. 17.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-?w from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 275 a force-type breakpoint waits for the current instruction to ?ish and then acts upon the breakpoint request. the usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminology is used in two contexts within the debug module. the ?st context refers to breakpoint requests from the debug module to the cpu. the second refers to match signals from the comparators to the debugger control logic. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executing the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is quali?d by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 17.3.5 trigger modes the trigger mode controls the overall behavior of a debug run. the 4-bit trg ?ld in the dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt register, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fifo begins storing data when the quali?d trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed until the quali?d trigger is detected (end trigger). a debug run is started by writing a 1 to the arm bit in the dbgc register, which sets the armf ?g and clears the af and bf ?gs and the cnt bits in dbgs. a begin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event-only modes, the fifo stores change-of-?w addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not necessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full mode trigger because the opcode value is normally known at a particular address. the following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali?d with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the signal from the comparator with optional r/w quali?ation is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 276 freescale semiconductor a-only ?trigger when the address matches the value in comparator a a or b ?trigger when the address matches either the value in comparator a or the value in comparator b a then b ?trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any number of cycles after the a match and before the b match. a and b data (full mode) ?this is called a full mode because address, data, and r/w (optionally) must match within the same bus cycle to cause a trigger event. comparator a checks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. a and not b data (full mode) ?address must match comparator a, data must not match the low half of comparator b, and r/w must match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. event-only b (store data) ?trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) after the address has matched the value in comparator a, a trigger event occurs each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ?a trigger occurs when the address is either less than the value in comparator a or greater than the value in comparator b.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 277 17.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 17.3.5, ?rigger modes , to be used to generate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it enters the instruction queue. if a tagged opcode reaches the end of the pipe, the cpu executes a bgnd instruction to go to active background mode rather than executing the tagged opcode. a force-type breakpoint causes the cpu to ?ish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 17.4 register de?ition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all dbg registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 17.4.1 bdc registers and control bits the bdc has two registers: the bdc status and control register (bdcscr) is an 8-bit register containing control and status bits for the background debug controller. the bdc breakpoint match register (bdcbkpt) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have addresses and cannot be accessed by user programs). some of the bits in the bdcscr have write limitations; otherwise, these registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents the ambiguous condition of the control bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be written by the write_control serial bdc command. the clock switch (clksw) control bit may be read or written at any time.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 278 freescale semiconductor 17.4.1.1 bdc status and control register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 17-5. bdc status and control register (bdcscr) table 17-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ?typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ?this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ?if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ?when fts = 1, a breakpoint is requested whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagged. if this tagged opcode ever reaches the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ?clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 279 17.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hardware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and con?ure the breakpoint logic. dedicated serial bdc commands (read_bkpt and write_bkpt) are used to read and write the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 17.2.4, ?dc hardware breakpoint . 17.4.2 system background debug force reset register (sbdfr) this register contains a single write-only control bit. a serial background mode command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ?when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force the target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a background command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status this status bit is set if a memory access command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically, the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not con?ct with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status this status bit is not used in the mc9s08sh8 because it does not have any slow access memory. 0 memory access did not con?ct with a slow memory access 1 memory access command failed because cpu was not ?ished with a slow memory access table 17-2. bdcscr register field descriptions (continued) field description
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 280 freescale semiconductor figure 17-6. system background debug force reset register (sbdfr) 17.4.3 dbg registers and control bits the debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal application programs. these registers are rarely if ever accessed by normal user application programs with the possible exception of a rom patching mechanism that uses the breakpoint logic. 17.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high-order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low-order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high-order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low-order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. reset 00000000 = unimplemented or reserved table 17-3. sbdfr register field description field description 0 bdfr background debug force reset a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 281 17.4.3.5 debug fifo high register (dbgfh) this register provides read-only access to the high-order eight bits of the fifo. writes to this register have no meaning or effect. in the event-only trigger modes, the fifo only stores data into the low-order byte of each fifo word, so this register is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 17.4.3.6 debug fifo low register (dbgfl) this register provides read-only access to the low-order eight bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the next available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into the fifo (high-order half of each fifo word is unused). when reading 8-bit words out of the fifo, simply read dbgfl repeatedly to get successive bytes of data from the fifo. it isnt necessary to read dbgfh in this case. do not attempt to read data from the fifo while it is still armed (after arming but before the fifo is ?led or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequencing of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodically, external host software can develop a pro?e of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the ?st read. to use the pro?ing feature, read the fifo eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 282 freescale semiconductor 17.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset 00000000 figure 17-7. debug control register (dbgc) table 17-4. dbgc register field descriptions field description 7 dbgen debug module enable ?used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0 dbg disabled 1 dbg enabled 6 arm arm control controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ?controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparator(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fifo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a when rwaen = 1, this bit determines whether a read or a write access quali?s comparator a. when rwaen = 0, rwa and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ?controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b when rwben = 1, this bit determines whether a read or a write access quali?s comparator b. when rwben = 0, rwb and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ?controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 283 17.4.3.8 debug trigger register (dbgt) this register can be read any time, but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w reset 00000000 = unimplemented or reserved figure 17-8. debug trigger register (dbgt) table 17-5. dbgt register field descriptions field description 7 trgsel trigger type ?controls whether the match outputs from comparators a and b are quali?d with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparator a or b must propagate through the opcode tracking logic and a trigger event is only signalled to the fifo logic if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select controls whether the fifo starts ?ling at a trigger or ?ls in a circular manner until a trigger ends the capture of information. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ?selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ?1111 (no trigger)
chapter 17 development support mc9s08sh8 mcu series data sheet, rev. 1 284 freescale semiconductor 17.4.3.9 debug status register (dbgs) this is a read-only status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w reset 00000000 = unimplemented or reserved figure 17-9. debug status register (dbgs) table 17-6. dbgs register field descriptions field description 7 af trigger match a flag ?af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ?bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag while dbgen = 1, this status bit is a read-only image of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trace) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count these bits are cleared at the start of a debug run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping track of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 285 appendix a electrical characteristics a.1 introduction this section contains electrical and timing speci?ations for the mc9s08sh8 series of microcontrollers available at the time of publication. a.2 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate: note the classi?ation is shown in the column labeled ??in the parameter tables where appropriate. a.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits speci?d in table a-2 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused table a-1. parameter classi?ations p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 286 freescale semiconductor inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table a-2. absolute maximum ratings rating symbol value unit supply voltage v dd ?.3 to +5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?5 to 150 c
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 287 a.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table a-3. thermal characteristics num c rating symbol value unit 1 operating temperature range (packaged) c m t a t l to t h ?0 to 85 ?0 to 125 c 2 maximum junction temperature t j 135 c thermal resistance 1,2 single-layer board 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ?w, power dissipation of other components on the board, and board thermal resistance. 2 junction to ambient natural convection 3 d 8-pin nb soic ja 167 c/w 16-pin tssop 123 20-pin pdip 68 20-pin tssop 115 24-pin qfn 110 thermal resistance 1,2 four-layer board 8-pin nb soic 115 c/w 4 d 16-pin tssop 75 20-pin pdip ja 49 20-pin tssop 76 24-pin qfn 42
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 288 freescale semiconductor the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273c) eqn. a-2 solving equation a-1 and equation a-2 for k gives: k = p d (t a + 273c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation a-1 and equation a-2 iteratively for any value of t a .
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 289 a.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. quali?ation tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table a-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table a-5. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 v 2 charge device model (cdm) v cdm 500 v 3 latch-up current at t a = 125ci lat 100 ma
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 290 freescale semiconductor a.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table a-6. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage v dd 2.7 5.5 v 2 c all i/o pins, 5 v, i load = ? ma v dd ?1.5 p low-drive strength 5 v, i load = ? ma v dd ?0.8 c output high v oh 3 v, i load = ? ma v dd ?0.8 v c voltage 5 v, i load = ?0 ma v dd ?1.5 p all i/o pins, 5 v, i load = ?0 ma v dd ?0.8 c high-drive strength 3 v, i load = ? ma v dd ?0.8 3c output high current max total i oh for all ports i oht v out < v dd 0 ?00 ma 4 c all i/o pins 5 v, i load = 4 ma 1.5 p low-drive strength 5 v, i load = 2 ma 0.8 c output low v ol 3 v, i load = 1 ma 0.8 v c voltage 5 v, i load = 20 ma 1.5 p all i/o pins 5 v, i load = 10 ma 0.8 c high-drive strength 3 v, i load = 5 ma 0.8 5c output low current max total i ol for all ports i olt v out > v ss 0 100 ma 6 p input high voltage; all digital inputs v ih 5v 0.65 x v dd v c 3v 0.7 x v dd 7 p input low voltage; all digital inputs v il 5v 0.35 x v dd v c 3v 0.35 x v dd 8 c input hysteresis v hys 0.06 x v dd mv 9 p input leakage current (per pin) | i in | v in = v dd or v ss 0.1 1 a 10 p hi-z (off-state) leakage current (per pin) input/output port pins | i oz | v in = v dd or v ss , 0.1 1 a ptb5/irq/tclk/ reset , ptb6/sda/xtal pins v in = v dd or v ss ?.2 2 a 11 pullup or pulldown 2 resistors; when enabled p i/o pins r pu ,r pd 17 37 52 k c reset 3 r pu 17 37 52 k 12 d dc injection current 4, 5, 6, 7 single pin limit v in > v dd 0?ma i ic v in < v ss , 0 ?.2 ma total mcu limit, includes v in > v dd 0 25 ma sum of all stressed pins v in < v ss ,0 5m a 13 d input capacitance, all pins c in 8pf 14 d ram retention voltage v ram 0.6 1.0 v
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 291 15 d por re-arm voltage 8 v por 0.9 1.4 2.0 v 16 d por re-arm time 9 t por 10 s 17 p low-voltage detection threshold high range v dd falling v dd rising v lvd1 3.9 4.0 4.0 4.1 4.1 4.2 v 18 low-voltage detection threshold low range v dd falling v dd rising v lvd0 2.48 2.54 2.56 2.62 2.64 2.70 v p 19 low-voltage warning threshold high range 1 v dd falling v dd rising v lvw3 . 4.5 4.6 4.6 4.7 4.7 4.8 v p 20 low-voltage warning threshold high range 0 v dd falling v dd rising v lvw2 4.2 4.3 4.3 4.4 4.4 4.5 v p 21 low-voltage warning threshold low range 1 v dd falling v dd rising v lvw1 2.84 2.90 2.92 2.98 3.00 3.06 v p 22 low-voltage warning threshold low range 0 v dd falling v dd rising v lvw0 2.66 2.72 2.74 2.80 2.82 2.88 v p 23 t low-voltage inhibit reset/recover hysteresis v hys 5 v 100 mv 3 v 60 24 p bandgap voltage reference 10 v bg 1.18 1.20 1.21 v 1 typical values are measured at 25 c. characterized, not tested. 2 when irq or a pin interrupt is con?ured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 the speci?d resistor value is the actual value internal to the device. the pullup value may measure higher when measured externally on the pin. 4 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 the reset pin does not have a clamp diode to v dd . do not drive this pin above v dd . 8 maximum is highest voltage that por will occur. 9 simulated, not tested 10 factory trimmed at v dd = 5.0 v, temp = 25 c table a-6. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 292 freescale semiconductor figure a-1. typical v ol vs i ol , high drive strength figure a-2. typical v ol vs i ol , low drive strength v ol (v) i ol (ma) 20 15 10 5 025 0 0.5 1 1.5 2 a) v dd = 5v, high drive v ol (v) i ol (ma) 8642 010 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125?c 25?c ?0?c max 0.8v@5ma max 1.5v@20ma 125?c 25?c ?0?c v ol (v) i ol (ma) 4321 05 0 0.5 1 1.5 2 125?c 25?c ?0?c a) v dd = 5v, low drive v ol (v) i ol (ma) 1.6 1.2 0.8 0.4 02. 0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125?c 25?c ?0?c max 0.8v@1ma max 1.5v@4ma
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 293 figure a-3. typical v dd ?v oh vs i oh , high drive strength figure a-4. typical v dd ?v oh vs i oh , low drive strength i oh (ma) ?0 ?5 ?0 ?0 ?5 0 0.5 1 1.5 2 125?c 25?c ?0?c a) v dd = 5v, high drive i oh (ma) ? ? ? ?0 ?0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125?c 25?c ?0?c max 0.8v@ ?ma max 1.5v@ ?0ma v dd ?v oh (v) v dd ?v oh (v) v dd ?v oh (v) i oh (ma) ? ? ? ? 05 0 0.5 1 1.5 2 125?c 25?c ?0?c a) v dd = 5v, low drive i oh (ma) ?.6 ?.2 ?.8 ?.4 0 ?.0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125?c 25?c ?0?c max 0.8v@ ?ma max 1.5v@ ?ma v dd ?v oh (v)
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 294 freescale semiconductor a.7 supply current characteristics this section includes information about power supply current in various operating modes. table a-7. supply current characteristics num c parameter symbol v dd (v) typ 1 max 2 unit 1 c run supply current 3 measured at (cpu clock = 4 mhz, f bus = 2 mhz) ri dd 5 1.1 1.5 ma c 3 1 1.5 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 5 3.9 5 ma c 3 3.9 5 3 c run supply current 4 measured at (cpu clock = 32 mhz, f bus = 16 mhz) ri dd 5 7.25 7.7 ma c 3 7.15 7.6 4 stop3 mode supply current s3i dd c ?0 c (c & m suf? ) 5 1.1 a p2 5 c (all parts) 1.5 p 5 85 c (c suf? only ) 9.0 22 p 5 125 c (m suf? only) 45.2 tbd c c and m suf? ?0 c 3 1.0 a c all parts 25 c 1.4 c c suf? only 85 c 7.8 19 c m suf? only 125 c 40.1 95 5 stop2 mode supply current s2i dd c c and m suf? ?0 c 5 1.1 a p all parts 25 c 1.4 p 5 c suf? only 85 c 6.8 22 p 5 m suf? only 125 c 32.7 tbd c c and m suf? ?0 c 3 1.0 a c all parts 25 c 1.3 c c suf? only 85 c 5.8 16 c m suf? only 125 c 28.3 95 6c rtc adder to stop2 or stop3 6 s23i ddrti 5 300 500 na 3 300 500 na 7 c lvd adder to stop3 (lvde = lvdse = 1) s3i ddlvd 5 110 180 a 3 90 160 a 8c adder to stop3 for oscillator enabled 7 (erefsten =1) s3i ddosc 5, 3 58 a
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 295 figure a-5. typical run i dd vs. bus frequency (v dd = 5v) 1 typical values are based on characterization data at 25 c. see figure a-5 through figure a-7 for typical curves across voltage/temperature. 2 max values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 all modules except adc active, ics con?ured for fbe, and does not include any dc loads on port pins. 4 all modules except adc active, ics con?ured for fei, and does not include any dc loads on port pins. 5 stop currents are tested in production for 25 c on all parts. tests at other temperatures depend upon the part number suf? and maturity of the product. freescale may eliminate a test insertion at a particular temperature from the production test ?w once suf?ient data has been collected and is approved. 6 most customers are expected to ?d that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 7 values given under the following conditions: low range operation (range = 0) with a 32.768khz crystal and low power mode (hgo = 0). run i dd (ma) f bus (mhz) 8 421 01 6 0 2 4 10 20 6 8 fei fbelp
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 296 freescale semiconductor figure a-6. typical run i dd vs. temperature (v dd = 5v; f bus = 8mhz) figure a-7. typical stop i dd vs. temperature (v dd = 5v) run i dd (ma) temperature ( ?c ) 85 25 0 ?0 105 0 1 2 5 125 3 4 stop i dd (a) temperature ( ?c ) 85 25 0 ?0 105 0 10 20 50 125 30 40 stop2 stop3
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 297 a.8 external oscillator (xosc) characteristics table a-8. oscillator electrical speci?ations (temperature range = ?0 to 125 c ambient) nu m c rating symbol min typ 1 1 typical data was characterized at 5.0 v, 25 c or is recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) f lo 32 38.4 khz high range (range = 1) fee or fbe mode 2 2 the input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. f hi 1 5 mhz high range (range = 1, hgo = 1) fbelp mode f hi-hgo 1 16 mhz high range (range = 1, hgo = 0) fbelp mode f hi-lp 1 8 mhz 2 load capacitors c 1, c 2 see crystal or resonator manufacturer? recommendation. 3 feedback resistor r f m low range (32 khz to 100 khz) 10 high range (1 mhz to 16 mhz) 1 4 series resistor r s k low range, low gain (range = 0, hgo = 0) 0 low range, high gain (range = 0, hgo = 1) 100 high range, low gain (range = 1, hgo = 0) 0 high range, high gain (range = 1, hgo = 1) 8 mhz 0 0 4 mhz 0 10 1 mhz 0 20 5t crystal start-up time 3 3 this parameter is characterized and not tested on each device. proper pc board layout procedures must be followed to achieve speci?ations. ms low range, low gain (range = 0, hgo = 0) t cstl-lp 200 low range, high gain (range = 0, hgo = 1) t cstl-hgo 400 high range, low gain (range = 1, hgo = 0) 4 4 4 mhz crystal t csth-lp ? high range, high gain (range = 1, hgo = 1) 4 t csth-hgo ?0 6t square wave input clock frequency (erefs = 0, erclken = 1) f extal fee or fbe mode 2 0.03125 5 mhz fbelp mode 0 40 mhz
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 298 freescale semiconductor mcu extal xtal crystal or resonator r s c 2 r f c 1
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 299 a.9 internal clock source (ics) characteristics table a-9. ics frequency speci?ations (temperature range = ?0 to 125 c ambient) nu m c rating symbol min typical max unit 1p internal reference frequency - factory trimmed at v dd = 5 v and temperature = 25 c f int_ft 31.25 khz 2p internal reference frequency - untrimmed 1 1 trim register at default value (0x80) and ftrim control bit at default value (0x0). f int_ut 25 36 41.66 khz 3 p internal reference frequency - user trimmed f int_t 31.25 39.0625 khz 4 d internal reference startup time t irefst 55 100 s 5 dco output frequency range - untrimmed 1 value provided for reference: f dco_ut = 1024 f int_ut f dco_ut 25.6 36.86 42.66 mhz 6 d dco output frequency range - trimmed f dco_t 32 40 mhz 7d resolution of trimmed dco output frequency at ?ed voltage and temperature (using ftrim) f dco_res_t 0.1 0.2 %f dco 8d resolution of trimmed dco output frequency at ?ed voltage and temperature (not using ftrim) f dco_res_t 0.2 0.4 %f dco 9d total deviation from actual trimmed dco output frequency over voltage and temperature f dco_t + 0.5 ?1.0 2 %f dco 10 d total deviation of trimmed dco output frequency over ?ed voltage and temperature range of 0 c to 70 c f dco_t 0.5 1 %f dco 11 d fll acquisition time 2 2 this speci?ation applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this speci?ation assumes it is already running. t acquire 1ms 12 d dco output clock long term jitter (over 2ms interval) 3 3 jitter is the average deviation from the programmed frequency measured over the speci?d interval at maximum f bus . measurements are made with the device powered by ?tered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. c jitter 0.02 0.2 %f dco
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 300 freescale semiconductor a.10 analog comparator (acmp) electricals table a-10. analog comparator electrical speci?ations num c rating symbol min typical max unit 1 supply voltage v dd 2.7 5.5 v 2 c/t supply current (active) i ddac ?035 a 3 d analog input voltage v ain v ss ?0.3 v dd v 4 d analog input offset voltage v aio 20 40 mv 5d analog comparator hysteresis v h 3.0 6.0 20.0 mv 6 d analog input leakage current i alkg -- -- 1.0 a 7 d analog comparator initialization delay t ainit 1.0 s
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 301 a.11 adc characteristics figure a-8. adc input impedance equivalency diagram table a-11. adc operating conditions characteristic conditions symb min typ 1 1 typical values assume v ddad = v dd = 5.0v, temp = 25 c, fadck=1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v ddad 2.7 5.5 v input voltage v adin v refl ? refh v input capacitance c adin 4.5 5.5 pf input resistance r adin ? 5 k analog source resistance 10 bit mode f adck > 4mhz f adck < 4mhz r as 5 10 k external to mcu 8 bit mode (all valid f adck ) 1 0 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 + + v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 302 freescale semiconductor table a-12. adc characteristics characteristic conditions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ti dd + i ddad 133 a adc current only supply current adlpc=1 adlsmp=0 adco=1 ti dd + i ddad 218 a adc current only supply current adlpc=0 adlsmp=1 adco=1 ti dd + i ddad 327 a adc current only supply current adlpc=0 adlsmp=0 adco=1 pi dd + i ddad 0.582 1 ma adc current only adc asynchronous clock source high speed (adlpc=0) pf adack 2 3.3 5 mhz t adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) dt adc ?0 adck cycles see adc chapter for conversion time variances long sample (adlsmp=1) 40 sample time short sample (adlsmp=0) dt ads 3.5 adck cycles long sample (adlsmp=1) 23.5 total unadjusted error (includes quantization) 10 bit mode pe tue 1.5 3.5 lsb 2 8 bit mode 0.7 1.5 lsb 2 differential non-linearity 10 bit mode p dnl 0.5 1.0 lsb 2 8 bit mode 0.3 0.5 monotonicity and no-missing-codes guaranteed integral non-linearity 10 bit mode t inl 0.5 1.0 lsb 2 8 bit mode 0.3 0.5 zero-scale error 10 bit mode pe zs 1.5 2.5 lsb 2 8 bit mode 0.5 0.7 full-scale error (v adin = v dd ) 10 bit mode te fs 0 1.0 1.5 lsb 2 8 bit mode 0 0.5 0.5 quantization error 10 bit mode de q 0.5 lsb 2 8 bit mode 0.5 input leakage error 10 bit mode de il 0 0.2 2.5 lsb 2 pad leakage 2 * r as 8 bit mode 0 0.1 1
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 303 temp sensor slope ?0 c to 25 c dm 3.266 mv/c 25 c to 125c 3.638 temp sensor voltage 25 cd v temp25 1.396 mv 1 typical values assume v dd = 5.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 based on input pad leakage current. refer to pad electricals. table a-12. adc characteristics (continued) characteristic conditions c symb min typ 1 max unit comment
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 304 freescale semiconductor a.12 ac characteristics this section describes ac timing characteristics for each peripheral system. a.12.1 control timing figure a-9. reset timing table a-13. control timing nu m c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc 20 mhz 2 d internal low power oscillator period t lpo 800 1500 s 3d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 100 ns 4d reset low drive 3 3 when any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t cyc . after por reset the bus clock frequency changes to the untrimmed dco frequency (f reset = (f dco_ut )/4) because trim is reset to 0x80 and ftrim is reset to 0, and there is an extra divide-by-two because bdiv is reset to 0:1. after other resets trim stays at the pre-reset value. t rstdrv 66 x t cyc ?s 8d pin interrupt pulse width asynchronous path 2 synchronous path 5 t ilih, t ihil 100 1.5 x t cyc ns 9c port rise and fall time low output drive (ptxds = 0) (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?0 c to 125c. t rise , t fall 40 75 ns port rise and fall time high output drive (ptxds = 1) (load = 50 pf) 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall 11 35 ns t extrst reset pin
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 305 figure a-10. irq/pin interrupt timing t ihil irq/pin interrupts t ilih irq/pin interrupts
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 306 freescale semiconductor a.12.2 tpm/mtim module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure a-11. timer external clock figure a-12. timer input capture pulse table a-14. tpm input timing num c rating symbol min max unit 1 external clock frequency (1/t tclk )f tclk dc f bus /4 mhz 2 external clock period t tclk 4 t cyc 3 external clock high time t clkh 1.5 t cyc 4 external clock low time t clkl 1.5 t cyc 5 input capture pulse width t icpw 1.5 t cyc t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 307 a.12.3 spi table a-15 and figure a-13 through figure a-16 describe the timing requirements for the spi system. table a-15. spi electrical characteristic num 1 1 refer to figure a-13 through figure a-16 . c rating 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit 1 d cycle time master slave t sck t sck 2 4 2048 t cyc t cyc 2 d enable lead time master slave t lead t lead 1/2 1/2 t sck t sck 3 d enable lag time master slave t lag t lag 1/2 1/2 t sck t sck 4 d clock (spsck) high time master and slave t sckh 1/2 t sck ?25 ns 5 d clock (spsck) low time master and slave t sckl 1/2 t sck ?25 ns 6 d data setup time (inputs) master slave t si(m) t si(s) 30 30 ns ns 7 d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ns ns 8 d access time, slave 3 3 time to data active from high-impedance state. t a 04 0n s 9 d disable time, slave 4 4 hold time to high-impedance state. t dis ? 0n s 10 d data setup time (outputs) master slave t so t so 25 25 ns ns 11 d data hold time (outputs) master slave t ho t ho ?0 ?0 ns ns 12 d operating frequency master slave f op f op f bus /2048 dc 5 5 f bus /4 5 maximum baud rate must be limited to 5 mhz due to input ?ter characteristics. mhz
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 308 freescale semiconductor figure a-13. spi master timing (cpha = 0) figure a-14. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 309 figure a-15. spi slave timing (cpha = 0) figure a-16. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 310 freescale semiconductor a.13 flash speci?ations this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the memory section. table a-16. flash characteristics num c characteristic symbol min typical max unit 1 supply voltage for program/erase v prog/erase 2.7 5.5 v 2 supply voltage for read operation v read 2.7 5.5 v 3 internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz 4 internal fclk period (1/f fclk )t fcyc 5 6.67 s 5 byte program time (random location) 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t prog 9t fcyc 6 byte program time (burst mode) 2 t burst 4t fcyc 7 page erase time 2 t page 4000 t fcyc 8 mass erase time 2 t mass 20,000 t fcyc 9c program/erase endurance 3 t l to t h = ?0c to +125 c t = 25 c 3 typical endurance for flash is based on the intrinsic bit cell performance. for additional information on how freescale de?es typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory. n flpe 10,000 100,000 cycles 10 c data retention 4 4 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 years
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 311 a.14 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation all play a signi?ant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance speci?ally targeted at optimizing emc performance. a.14.1 radiated emissions microcontroller radiated rf emissions are measured from 150 khz to 1 ghz using the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two package orientations (north and east). the maximum radiated rf emissions of the tested con?uration in all orientations are less than or equal to the reported emissions levels. a.14.2 conducted transient susceptibility microcontroller transient conducted susceptibility is measured in accordance with an internal freescale test method. the measurement is performed with the microcontroller installed on a custom emc evaluation board and running specialized emc test software designed in compliance with the test method. the conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. the transient waveform and injection methodology is based on iec 61000-4-4 (eft/b). the transient voltage required to cause performance degradation on any pin in the tested con?uration is greater than or equal to the reported levels unless otherwise indicated by footnotes below table a-18 . table a-17. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on quali?ation test results. unit radiated emissions, electric ?ld v re_tem v dd = 5 v t a = +25 o c package type 16-tssop 0.15 ?50 mhz 4 mhz crystal 16 mhzbus 0 dbv 50 ?150 mhz 0 150 ?500 mhz ? 500 ?1000 mhz ? iec level n sae level 1
appendix a electrical characteristics mc9s08sh8 mcu series data sheet, rev. 1 312 freescale semiconductor the susceptibility performance classi?ation is described in table a-19 . table a-18. conducted susceptibility, eft/b parameter symbol conditions f osc /f bus result amplitude 1 (min) 1 data based on quali?ation test results. not tested in production. unit conducted susceptibility, electrical fast transient/burst (eft/b) v cs_eft v dd = 5 v t a = +25 o c package type 16-tssop 4 mhz crystal 16 mhz bus a4 kv b n/a c n/a d n/a table a-19. susceptibility performance classi?ation result performance criteria a no failure the mcu performs as designed during and after exposure. b self-recovering failure the mcu does not perform as designed during exposure. the mcu returns automatically to normal operation after exposure is removed. c soft failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the reset pin is asserted. d hard failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the power to the mcu is cycled. e damage the mcu does not perform as designed during and after exposure. the mcu cannot be returned to proper operation due to physical damage or other permanent performance degradation.
mc9s08sh8 mcu series data sheet, rev. 1 freescale semiconductor 313 appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering information for mc9s08sh8 and MC9S08SH4 devices. b.1.1 device numbering scheme table b-1. device numbering system device number 1 1 see table 1-1 for a complete description of modules included on each device. memory available packages 2 2 see table b-2 for package information. flash ram 24-pin 20-pin 16-pin 8-pin s9s08sh8 8k 512 24-qfn 20 pdip 20 tssop 16 tssop 8 nb soic s9s08sh4 4k 256 s 9 s08 sh 8 e2 c tg r status - s = auto quali?d main memory type - 9 = flash-based core sh family memory size - 8 kbytes - 4 kbytes mask set identi?r - alpha character references wafer fab. - numeric character identi?s mask. temperature option - c = -40 to 85 c - m = -40 to 125 c package designator two letter descriptor (refer to table b-2 ). tape and reel suf? (optional )
appendix b ordering information and mechanical drawings mc9s08sh8 mcu series data sheet, rev. 1 314 freescale semiconductor b.2 mechanical drawings the following pages are mechanical speci?ations for mc9s08sh8 package options. see table b-2 for the document number for each package type. table b-2. package information pin count type designator document no. 24 qfn fk 98arl10605d 20 pdip pj 98asb42899b 20 tssop tj 98ash70169a 16 tssop tg 98ash70247a 8 nb soic sc 98asb42564b

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